changeset 3cf8e71257e0 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=3cf8e71257e0 description: stats: Fix all stats usages to deal with template fixes
diffstat: 50 files changed, 486 insertions(+), 486 deletions(-) src/arch/alpha/kernel_stats.hh | 12 +-- src/arch/alpha/tlb.hh | 22 ++--- src/arch/mips/tlb.hh | 16 ++-- src/base/hybrid_pred.hh | 12 +-- src/base/sat_counter.hh | 12 +-- src/cpu/base.hh | 2 src/cpu/inorder/cpu.hh | 14 +-- src/cpu/inorder/pipeline_stage.hh | 14 +-- src/cpu/inorder/resource.hh | 2 src/cpu/inorder/resources/bpred_unit.hh | 16 ++-- src/cpu/inorder/resources/branch_predictor.hh | 4 - src/cpu/inorder/resources/execution_unit.hh | 4 - src/cpu/inorder/resources/inst_buffer.hh | 2 src/cpu/inorder/resources/mult_div_unit.hh | 4 - src/cpu/memtest/memtest.hh | 6 - src/cpu/o3/bpred_unit.hh | 16 ++-- src/cpu/o3/commit.hh | 28 +++---- src/cpu/o3/cpu.hh | 8 +- src/cpu/o3/decode.hh | 20 ++--- src/cpu/o3/fetch.hh | 24 +++--- src/cpu/o3/iew.hh | 54 +++++++------- src/cpu/o3/inst_queue.hh | 38 +++++----- src/cpu/o3/lsq_unit.hh | 20 ++--- src/cpu/o3/mem_dep_unit.hh | 8 +- src/cpu/o3/rename.hh | 38 +++++----- src/cpu/ozone/back_end.hh | 92 ++++++++++++------------- src/cpu/ozone/cpu.hh | 4 - src/cpu/ozone/front_end.hh | 40 +++++----- src/cpu/ozone/inorder_back_end.hh | 2 src/cpu/ozone/inst_queue.hh | 32 ++++---- src/cpu/ozone/lsq_unit.hh | 2 src/cpu/ozone/lw_back_end.hh | 84 +++++++++++----------- src/cpu/ozone/lw_lsq.hh | 4 - src/cpu/simple/base.hh | 14 +-- src/cpu/thread_state.hh | 4 - src/dev/copy_engine.hh | 4 - src/dev/etherdevice.hh | 64 ++++++++--------- src/dev/ide_disk.hh | 12 +-- src/dev/sinic.hh | 38 +++++----- src/kern/kernel_stats.hh | 16 ++-- src/mem/cache/base.hh | 32 ++++---- src/mem/cache/prefetch/base.hh | 18 ++-- src/mem/cache/tags/base.hh | 10 +- src/mem/cache/tags/fa_lru.hh | 6 - src/mem/cache/tags/iic.hh | 14 +-- src/mem/cache/tags/iic_repl/gen.hh | 6 - src/mem/dram.hh | 36 ++++----- src/sim/faults.hh | 2 src/sim/process.hh | 2 src/unittest/stattest.cc | 38 +++++----- diffs (truncated from 1953 to 300 lines): diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/kernel_stats.hh --- a/src/arch/alpha/kernel_stats.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/arch/alpha/kernel_stats.hh Thu Mar 05 19:09:53 2009 -0800 @@ -62,15 +62,15 @@ void changeMode(cpu_mode newmode, ThreadContext *tc); private: - Stats::Vector<> _callpal; -// Stats::Vector<> _faults; + Stats::Vector _callpal; +// Stats::Vector _faults; - Stats::Vector<> _mode; - Stats::Vector<> _modeGood; + Stats::Vector _mode; + Stats::Vector _modeGood; Stats::Formula _modeFraction; - Stats::Vector<> _modeTicks; + Stats::Vector _modeTicks; - Stats::Scalar<> _swap_context; + Stats::Scalar _swap_context; public: Statistics(System *system); diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/alpha/tlb.hh --- a/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/arch/alpha/tlb.hh Thu Mar 05 19:09:53 2009 -0800 @@ -121,9 +121,9 @@ class ITB : public TLB { protected: - mutable Stats::Scalar<> hits; - mutable Stats::Scalar<> misses; - mutable Stats::Scalar<> acv; + mutable Stats::Scalar hits; + mutable Stats::Scalar misses; + mutable Stats::Scalar acv; mutable Stats::Formula accesses; public: @@ -139,14 +139,14 @@ class DTB : public TLB { protected: - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula acv; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/arch/mips/tlb.hh --- a/src/arch/mips/tlb.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/arch/mips/tlb.hh Thu Mar 05 19:09:53 2009 -0800 @@ -96,14 +96,14 @@ void nextnlu() { if (++nlu >= size) nlu = 0; } MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; - mutable Stats::Scalar<> read_hits; - mutable Stats::Scalar<> read_misses; - mutable Stats::Scalar<> read_acv; - mutable Stats::Scalar<> read_accesses; - mutable Stats::Scalar<> write_hits; - mutable Stats::Scalar<> write_misses; - mutable Stats::Scalar<> write_acv; - mutable Stats::Scalar<> write_accesses; + mutable Stats::Scalar read_hits; + mutable Stats::Scalar read_misses; + mutable Stats::Scalar read_acv; + mutable Stats::Scalar read_accesses; + mutable Stats::Scalar write_hits; + mutable Stats::Scalar write_misses; + mutable Stats::Scalar write_acv; + mutable Stats::Scalar write_accesses; Stats::Formula hits; Stats::Formula misses; Stats::Formula invalids; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/base/hybrid_pred.hh --- a/src/base/hybrid_pred.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/base/hybrid_pred.hh Thu Mar 05 19:09:53 2009 -0800 @@ -62,12 +62,12 @@ // // Stats // - Stats::Scalar<> pred_one; //num_one_preds - Stats::Scalar<> pred_zero; //num_zero_preds - Stats::Scalar<> correct_pred_one; //num_one_correct - Stats::Scalar<> correct_pred_zero; //num_zero_correct - Stats::Scalar<> record_one; //num_one_updates - Stats::Scalar<> record_zero; //num_zero_updates + Stats::Scalar pred_one; //num_one_preds + Stats::Scalar pred_zero; //num_zero_preds + Stats::Scalar correct_pred_one; //num_one_correct + Stats::Scalar correct_pred_zero; //num_zero_correct + Stats::Scalar record_one; //num_one_updates + Stats::Scalar record_zero; //num_zero_updates Stats::Formula total_preds; Stats::Formula frac_preds_zero; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/base/sat_counter.hh --- a/src/base/sat_counter.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/base/sat_counter.hh Thu Mar 05 19:09:53 2009 -0800 @@ -64,13 +64,13 @@ unsigned *table; // Statistics - Stats::Scalar<> predicted_one; // Total predictions of one, preds_one - Stats::Scalar<> predicted_zero; // Total predictions of zero, preds_zero - Stats::Scalar<> correct_pred_one; // Total correct predictions of one, correct_one - Stats::Scalar<> correct_pred_zero; // Total correct predictions of zero, correct_zero + Stats::Scalar predicted_one; // Total predictions of one, preds_one + Stats::Scalar predicted_zero; // Total predictions of zero, preds_zero + Stats::Scalar correct_pred_one; // Total correct predictions of one, correct_one + Stats::Scalar correct_pred_zero; // Total correct predictions of zero, correct_zero - Stats::Scalar<> record_zero; //updates_zero - Stats::Scalar<> record_one; //updates_one + Stats::Scalar record_zero; //updates_zero + Stats::Scalar record_one; //updates_one Stats::Formula preds_total; Stats::Formula pred_frac_zero; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/base.hh --- a/src/cpu/base.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/base.hh Thu Mar 05 19:09:53 2009 -0800 @@ -304,7 +304,7 @@ public: // Number of CPU cycles simulated - Stats::Scalar<> numCycles; + Stats::Scalar numCycles; }; #endif // __CPU_BASE_HH__ diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/cpu.hh --- a/src/cpu/inorder/cpu.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/cpu.hh Thu Mar 05 19:09:53 2009 -0800 @@ -638,25 +638,25 @@ inline void tickThreadStats(); /** Per-Thread Tick */ - Stats::Vector<> threadCycles; + Stats::Vector threadCycles; /** Tick for SMT */ - Stats::Scalar<> smtCycles; + Stats::Scalar smtCycles; /** Stat for total number of times the CPU is descheduled. */ - Stats::Scalar<> timesIdled; + Stats::Scalar timesIdled; /** Stat for total number of cycles the CPU spends descheduled. */ - Stats::Scalar<> idleCycles; + Stats::Scalar idleCycles; /** Stat for the number of committed instructions per thread. */ - Stats::Vector<> committedInsts; + Stats::Vector committedInsts; /** Stat for the number of committed instructions per thread. */ - Stats::Vector<> smtCommittedInsts; + Stats::Vector smtCommittedInsts; /** Stat for the total number of committed instructions. */ - Stats::Scalar<> totalCommittedInsts; + Stats::Scalar totalCommittedInsts; /** Stat for the CPI per thread. */ Stats::Formula cpi; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/pipeline_stage.hh --- a/src/cpu/inorder/pipeline_stage.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/pipeline_stage.hh Thu Mar 05 19:09:53 2009 -0800 @@ -340,19 +340,19 @@ //@TODO: Use Stats for the pipeline stages /** Stat for total number of idle cycles. */ - //Stats::Scalar<> stageIdleCycles; + //Stats::Scalar stageIdleCycles; /** Stat for total number of blocked cycles. */ - //Stats::Scalar<> stageBlockedCycles; + //Stats::Scalar stageBlockedCycles; /** Stat for total number of normal running cycles. */ - //Stats::Scalar<> stageRunCycles; + //Stats::Scalar stageRunCycles; /** Stat for total number of unblocking cycles. */ - //Stats::Scalar<> stageUnblockCycles; + //Stats::Scalar stageUnblockCycles; /** Stat for total number of squashing cycles. */ - //Stats::Scalar<> stageSquashCycles; + //Stats::Scalar stageSquashCycles; /** Stat for total number of staged instructions. */ - //Stats::Scalar<> stageProcessedInsts; + //Stats::Scalar stageProcessedInsts; /** Stat for total number of squashed instructions. */ - //Stats::Scalar<> stageSquashedInsts; + //Stats::Scalar stageSquashedInsts; }; #endif diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resource.hh --- a/src/cpu/inorder/resource.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/resource.hh Thu Mar 05 19:09:53 2009 -0800 @@ -232,7 +232,7 @@ // ///////////////////////////////////////////////////////////////// /** Number of Instruction Requests the Resource Processes */ - Stats::Scalar<> instReqsProcessed; + Stats::Scalar instReqsProcessed; }; class ResourceEvent : public Event diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resources/bpred_unit.hh --- a/src/cpu/inorder/resources/bpred_unit.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/resources/bpred_unit.hh Thu Mar 05 19:09:53 2009 -0800 @@ -238,21 +238,21 @@ ReturnAddrStack RAS[ThePipeline::MaxThreads]; /** Stat for number of BP lookups. */ - Stats::Scalar<> lookups; + Stats::Scalar lookups; /** Stat for number of conditional branches predicted. */ - Stats::Scalar<> condPredicted; + Stats::Scalar condPredicted; /** Stat for number of conditional branches predicted incorrectly. */ - Stats::Scalar<> condIncorrect; + Stats::Scalar condIncorrect; /** Stat for number of BTB lookups. */ - Stats::Scalar<> BTBLookups; + Stats::Scalar BTBLookups; /** Stat for number of BTB hits. */ - Stats::Scalar<> BTBHits; + Stats::Scalar BTBHits; /** Stat for number of times the BTB is correct. */ - Stats::Scalar<> BTBCorrect; + Stats::Scalar BTBCorrect; /** Stat for number of times the RAS is used to get a target. */ - Stats::Scalar<> usedRAS; + Stats::Scalar usedRAS; /** Stat for number of times the RAS is incorrect. */ - Stats::Scalar<> RASIncorrect; + Stats::Scalar RASIncorrect; }; #endif // __CPU_INORDER_BPRED_UNIT_HH__ diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resources/branch_predictor.hh --- a/src/cpu/inorder/resources/branch_predictor.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/resources/branch_predictor.hh Thu Mar 05 19:09:53 2009 -0800 @@ -78,8 +78,8 @@ // RESOURCE STATISTICS // ///////////////////////////////////////////////////////////////// - Stats::Scalar<> predictedTaken; - Stats::Scalar<> predictedNotTaken; + Stats::Scalar predictedTaken; + Stats::Scalar predictedNotTaken; }; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resources/execution_unit.hh --- a/src/cpu/inorder/resources/execution_unit.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/resources/execution_unit.hh Thu Mar 05 19:09:53 2009 -0800 @@ -69,8 +69,8 @@ // RESOURCE STATISTICS // ///////////////////////////////////////////////////////////////// - Stats::Scalar<> predictedTakenIncorrect; - Stats::Scalar<> predictedNotTakenIncorrect; + Stats::Scalar predictedTakenIncorrect; + Stats::Scalar predictedNotTakenIncorrect; }; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resources/inst_buffer.hh --- a/src/cpu/inorder/resources/inst_buffer.hh Thu Mar 05 19:09:53 2009 -0800 +++ b/src/cpu/inorder/resources/inst_buffer.hh Thu Mar 05 19:09:53 2009 -0800 @@ -86,7 +86,7 @@ // ///////////////////////////////////////////////////////////////// /** Number of Instruction Requests the Resource Processes */ - Stats::Scalar<> instsBypassed; + Stats::Scalar instsBypassed; }; diff -r a4c935e9cf99 -r 3cf8e71257e0 src/cpu/inorder/resources/mult_div_unit.hh --- a/src/cpu/inorder/resources/mult_div_unit.hh Thu Mar 05 19:09:53 2009 -0800 _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev