changeset 044903442dcb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=044903442dcb
description:
alpha: get rid of all turbolaser remnants
diffstat:
8 files changed, 10 insertions(+), 62 deletions(-)
SConstruct | 2 +-
build_opts/ALPHA_FS | 1 -
build_opts/ALPHA_FS_TL | 2 --
src/arch/alpha/SConsopts | 4 ----
src/arch/alpha/ev5.hh | 13 -------------
src/arch/alpha/tlb.cc | 32 +++-----------------------------
src/dev/Uart.py | 5 -----
tests/SConscript | 13 ++++++-------
diffs (215 lines):
diff -r 0555121b5c5f -r 044903442dcb SConstruct
--- a/SConstruct Wed Apr 08 22:21:30 2009 -0700
+++ b/SConstruct Wed Apr 08 22:22:49 2009 -0700
@@ -698,7 +698,7 @@
)
# These variables get exported to #defines in config/*.hh (see src/SConscript).
-env.ExportVariables = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
+env.ExportVariables = ['FULL_SYSTEM', 'USE_FENV', \
'USE_MYSQL', 'NO_FAST_ALLOC', 'FAST_ALLOC_DEBUG', \
'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', \
'USE_CHECKER', 'TARGET_ISA', 'CP_ANNOTATE']
diff -r 0555121b5c5f -r 044903442dcb build_opts/ALPHA_FS
--- a/build_opts/ALPHA_FS Wed Apr 08 22:21:30 2009 -0700
+++ b/build_opts/ALPHA_FS Wed Apr 08 22:22:49 2009 -0700
@@ -1,2 +1,1 @@
FULL_SYSTEM = 1
-ALPHA_TLASER = 0
diff -r 0555121b5c5f -r 044903442dcb build_opts/ALPHA_FS_TL
--- a/build_opts/ALPHA_FS_TL Wed Apr 08 22:21:30 2009 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2 +0,0 @@
-FULL_SYSTEM = 1
-ALPHA_TLASER = 1
diff -r 0555121b5c5f -r 044903442dcb src/arch/alpha/SConsopts
--- a/src/arch/alpha/SConsopts Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/SConsopts Wed Apr 08 22:22:49 2009 -0700
@@ -31,7 +31,3 @@
Import('*')
all_isa_list.append('alpha')
-
-# Alpha can be compiled with Turbolaser support instead of Tsunami
-sticky_vars.Add(BoolVariable('ALPHA_TLASER',
- 'Model Alpha TurboLaser platform (vs. Tsunami)', False))
diff -r 0555121b5c5f -r 044903442dcb src/arch/alpha/ev5.hh
--- a/src/arch/alpha/ev5.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/ev5.hh Wed Apr 08 22:22:49 2009 -0700
@@ -33,17 +33,11 @@
#ifndef __ARCH_ALPHA_EV5_HH__
#define __ARCH_ALPHA_EV5_HH__
-#include "config/alpha_tlaser.hh"
#include "arch/alpha/isa_traits.hh"
namespace AlphaISA {
-#if ALPHA_TLASER
-const uint64_t AsnMask = ULL(0x7f);
-#else
const uint64_t AsnMask = ULL(0xff);
-#endif
-
const int VAddrImplBits = 43;
const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
const Addr VAddrUnImplMask = ~VAddrImplMask;
@@ -53,13 +47,8 @@
inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
-#if ALPHA_TLASER
-inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
-const int PAddrImplBits = 40;
-#else
inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
const int PAddrImplBits = 44; // for Tsunami
-#endif
const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
const Addr PAddrUncachedBit39 = ULL(0x8000000000);
const Addr PAddrUncachedBit40 = ULL(0x10000000000);
@@ -69,12 +58,10 @@
inline Addr
Phys2K0Seg(Addr addr)
{
-#if !ALPHA_TLASER
if (addr & PAddrUncachedBit43) {
addr &= PAddrUncachedMask;
addr |= PAddrUncachedBit40;
}
-#endif
return addr | K0SegBase;
}
diff -r 0555121b5c5f -r 044903442dcb src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/tlb.cc Wed Apr 08 22:22:49 2009 -0700
@@ -39,7 +39,6 @@
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
-#include "config/alpha_tlaser.hh"
#include "cpu/thread_context.hh"
using namespace std;
@@ -215,12 +214,7 @@
*/
-#if ALPHA_TLASER
- if (req->getPaddr() & PAddrUncachedBit39)
-#else
- if (req->getPaddr() & PAddrUncachedBit43)
-#endif
- {
+ if (req->getPaddr() & PAddrUncachedBit43) {
// IPR memory space not implemented
if (PAddrIprSpace(req->getPaddr())) {
return new UnimpFault("IPR memory space not implemented!");
@@ -228,11 +222,9 @@
// mark request as uncacheable
req->setFlags(Request::UNCACHEABLE);
-#if !ALPHA_TLASER
// Clear bits 42:35 of the physical address (10-2 in
// Tsunami manual)
req->setPaddr(req->getPaddr() & PAddrUncachedMask);
-#endif
}
// We shouldn't be able to read from an uncachable address in Alpha as
// we don't have a ROM and we don't want to try to fetch from a device
@@ -398,13 +390,7 @@
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
-#if ALPHA_TLASER
- if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->getVaddr()) == 2)
-#else
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
-#endif
- {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
// only valid in kernel mode
if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
mode_kernel) {
@@ -414,14 +400,11 @@
req->setPaddr(req->getVaddr() & PAddrImplMask);
-#if !ALPHA_TLASER
// sign extend the physical address properly
if (req->getPaddr() & PAddrUncachedBit40)
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
-#endif
-
} else {
// not a physical address: need to look up pte
int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
@@ -495,13 +478,7 @@
}
// Check for "superpage" mapping
-#if ALPHA_TLASER
- if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->getVaddr()) == 2)
-#else
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e)
-#endif
- {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
// only valid in kernel mode
if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
mode_kernel) {
@@ -515,14 +492,11 @@
req->setPaddr(req->getVaddr() & PAddrImplMask);
-#if !ALPHA_TLASER
// sign extend the physical address properly
if (req->getPaddr() & PAddrUncachedBit40)
req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
-#endif
-
} else {
if (write)
write_accesses++;
diff -r 0555121b5c5f -r 044903442dcb src/dev/Uart.py
--- a/src/dev/Uart.py Wed Apr 08 22:21:30 2009 -0700
+++ b/src/dev/Uart.py Wed Apr 08 22:22:49 2009 -0700
@@ -38,8 +38,3 @@
class Uart8250(Uart):
type = 'Uart8250'
-
-if build_env['ALPHA_TLASER']:
- class Uart8530(Uart):
- type = 'Uart8530'
-
diff -r 0555121b5c5f -r 044903442dcb tests/SConscript
--- a/tests/SConscript Wed Apr 08 22:21:30 2009 -0700
+++ b/tests/SConscript Wed Apr 08 22:22:49 2009 -0700
@@ -251,13 +251,12 @@
configs = []
if env['FULL_SYSTEM']:
if env['TARGET_ISA'] == 'alpha':
- if not env['ALPHA_TLASER']:
- configs += ['tsunami-simple-atomic',
- 'tsunami-simple-timing',
- 'tsunami-simple-atomic-dual',
- 'tsunami-simple-timing-dual',
- 'twosys-tsunami-simple-atomic',
- 'tsunami-o3', 'tsunami-o3-dual']
+ configs += ['tsunami-simple-atomic',
+ 'tsunami-simple-timing',
+ 'tsunami-simple-atomic-dual',
+ 'tsunami-simple-timing-dual',
+ 'twosys-tsunami-simple-atomic',
+ 'tsunami-o3', 'tsunami-o3-dual']
if env['TARGET_ISA'] == 'sparc':
configs += ['t1000-simple-atomic',
't1000-simple-timing']
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