[m5-dev] [PATCH] CPU: Make the CPU wait until initiateAcc finishes before calling completeAcc

[gblack]

# HG changeset patch
# User Gabe Black <gbl...@eecs.umich.edu>
# Date 1240729422 25200
# Node ID 284ff3c27bbddacf5763e7b5a54e99e4dcd1912a
# Parent  8652636856b3d24fb0088fb1af5f5dca5008d9c8
CPU: Make the CPU wait until initiateAcc finishes before calling completeAcc.

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -115,6 +115,8 @@
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
     previousTick = 0;
+    inInitiateAcc = false;
+    completionPkt = NULL;
     changeState(SimObject::Running);
 }
 
@@ -758,7 +760,13 @@
     if (curStaticInst &&
             curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
         // load or store: just send to dcache
+        inInitiateAcc = true;
         Fault fault = curStaticInst->initiateAcc(this, traceData);
+        inInitiateAcc = false;
+        if (completionPkt) {
+            completeDataAccess(completionPkt);
+            completionPkt = NULL;
+        }
         if (_status != Running) {
             // instruction will complete in dcache response callback
             assert(_status == DcacheWaitResponse ||
@@ -856,6 +864,10 @@
 void
 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 {
+    if (inInitiateAcc) {
+        completionPkt = pkt;
+        return;
+    }
     // received a response from the dcache: complete the load or store
     // instruction
     assert(!pkt->isError());
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -317,6 +317,9 @@
 
     Tick previousTick;
 
+    bool inInitiateAcc;
+    PacketPtr completionPkt;
+
   public:
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);
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