changeset 4f8af2f3185f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4f8af2f3185f
description:
        X86: Record the initial APIC ID which identifies an APIC in M5.
        The ID as exposed to software can be changed. Tracking those changes in 
M5
        would be cumbersome, especially since there's no guarantee the IDs will 
remain
        unique.

diffstat:

4 files changed, 23 insertions(+), 23 deletions(-)
src/arch/x86/interrupts.cc |   36 ++++++++++++++++--------------------
src/arch/x86/interrupts.hh |    2 ++
src/dev/x86/i82094aa.cc    |    2 +-
src/dev/x86/i82094aa.hh    |    6 ++++--

diffs (139 lines):

diff -r 9327451a8e7a -r 4f8af2f3185f src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc        Sun Apr 26 02:04:32 2009 -0700
+++ b/src/arch/x86/interrupts.cc        Sun Apr 26 02:06:21 2009 -0700
@@ -295,17 +295,21 @@
 void
 X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
 {
+    assert(newCPU);
+    if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
+        panic("Local APICs can't be moved between CPUs"
+                " with different IDs.\n");
+    }
     cpu = newCPU;
-    assert(cpu);
-    regs[APIC_ID] = (cpu->cpuId() << 24);
+    initialApicId = cpu->cpuId();
+    regs[APIC_ID] = (initialApicId << 24);
 }
 
 
 Tick
 X86ISA::Interrupts::recvMessage(PacketPtr pkt)
 {
-    uint8_t id = (regs[APIC_ID] >> 24);
-    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
+    Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
     assert(pkt->cmd == MemCmd::MessageReq);
     switch(offset)
     {
@@ -315,9 +319,6 @@
             DPRINTF(LocalApic,
                     "Got Trigger Interrupt message with vector %#x.\n",
                     message.vector);
-            // Make sure we're really supposed to get this.
-            assert((message.destMode == 0 && message.destination == id) ||
-                   (bits((int)message.destination, id)));
 
             requestInterrupt(message.vector,
                     message.deliveryMode, message.trigger);
@@ -354,10 +355,10 @@
 void
 X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
 {
-    uint8_t id = (regs[APIC_ID] >> 24);
     range_list.clear();
-    Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0),
-                                x86LocalAPICAddress(id, 0) + PageBytes);
+    Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
+                                x86LocalAPICAddress(initialApicId, 0) + 
+                                PageBytes);
     range_list.push_back(range);
     pioAddr = range.start;
 }
@@ -366,10 +367,10 @@
 void
 X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
 {
-    uint8_t id = (regs[APIC_ID] >> 24);
     range_list.clear();
-    range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
-                x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
+    range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
+                x86InterruptAddress(initialApicId, 0) +
+                PhysAddrAPICRangeSize));
 }
 
 
@@ -515,14 +516,9 @@
                 {
                     int numContexts = sys->numContexts();
                     pendingIPIs += (numContexts - 1);
-                    // We have no way to get at the thread context we're part
-                    // of, so we'll just have to go with the CPU for now.
-                    hack_once("Broadcast IPIs can't handle more than "
-                            "one context per CPU.\n");
-                    int myId = cpu->getContext(0)->contextId();
                     for (int i = 0; i < numContexts; i++) {
                         int thisId = sys->getThreadContext(i)->contextId();
-                        if (thisId != myId) {
+                        if (thisId != initialApicId) {
                             PacketPtr pkt = buildIntRequest(thisId, message);
                             if (timing)
                                 intPort->sendMessageTiming(pkt, latency);
@@ -589,7 +585,7 @@
     pendingInit(false), initVector(0),
     pendingStartup(false), startupVector(0),
     startedUp(false), pendingUnmaskableInt(false),
-    pendingIPIs(0)
+    pendingIPIs(0), cpu(NULL)
 {
     pioSize = PageBytes;
     memset(regs, 0, sizeof(regs));
diff -r 9327451a8e7a -r 4f8af2f3185f src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh        Sun Apr 26 02:04:32 2009 -0700
+++ b/src/arch/x86/interrupts.hh        Sun Apr 26 02:06:21 2009 -0700
@@ -191,6 +191,8 @@
 
     BaseCPU *cpu;
 
+    int initialApicId;
+
   public:
     /*
      * Params stuff.
diff -r 9327451a8e7a -r 4f8af2f3185f src/dev/x86/i82094aa.cc
--- a/src/dev/x86/i82094aa.cc   Sun Apr 26 02:04:32 2009 -0700
+++ b/src/dev/x86/i82094aa.cc   Sun Apr 26 02:06:21 2009 -0700
@@ -40,7 +40,7 @@
     extIntPic(p->external_int_pic)
 {
     // This assumes there's only one I/O APIC in the system
-    id = p->apic_id;
+    initialApicId = id = p->apic_id;
     assert(id <= 0xf);
     arbId = id;
     regSel = 0;
diff -r 9327451a8e7a -r 4f8af2f3185f src/dev/x86/i82094aa.hh
--- a/src/dev/x86/i82094aa.hh   Sun Apr 26 02:04:32 2009 -0700
+++ b/src/dev/x86/i82094aa.hh   Sun Apr 26 02:06:21 2009 -0700
@@ -68,6 +68,7 @@
     I8259 * extIntPic;
 
     uint8_t regSel;
+    uint8_t initialApicId;
     uint8_t id;
     uint8_t arbId;
 
@@ -103,8 +104,9 @@
     void getIntAddrRange(AddrRangeList &range_list)
     {
         range_list.clear();
-        range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
-                    x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
+        range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
+                    x86InterruptAddress(initialApicId, 0) +
+                    PhysAddrAPICRangeSize));
     }
 
     void writeReg(uint8_t offset, uint32_t value);
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