changeset 2bfd792b1cc0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2bfd792b1cc0
description:
X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset
into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the
time, but
it's much more likely that the group will stay consistent and the pain
will be
distributed evenly.
diffstat:
2 files changed, 19 insertions(+), 3 deletions(-)
src/dev/x86/i82094aa.cc | 20 +++++++++++++++++---
src/dev/x86/i82094aa.hh | 2 ++
diffs (49 lines):
diff -r 6cbdd76b93db -r 2bfd792b1cc0 src/dev/x86/i82094aa.cc
--- a/src/dev/x86/i82094aa.cc Sun Apr 26 02:09:27 2009 -0700
+++ b/src/dev/x86/i82094aa.cc Sun Apr 26 02:09:54 2009 -0700
@@ -38,7 +38,7 @@
X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
latency(p->pio_latency), pioAddr(p->pio_addr),
- extIntPic(p->external_int_pic)
+ extIntPic(p->external_int_pic), lowestPriorityOffset(0)
{
// This assumes there's only one I/O APIC in the system
initialApicId = id = p->apic_id;
@@ -189,8 +189,22 @@
apics.push_back(localApicIt->first);
}
}
- if (message.deliveryMode == DeliveryMode::LowestPriority) {
- panic("Lowest priority delivery mode is not implemented.\n");
+ if (message.deliveryMode == DeliveryMode::LowestPriority &&
+ apics.size()) {
+ // The manual seems to suggest that the chipset just does
+ // something reasonable for these instead of actually using
+ // state from the local APIC. We'll just rotate an offset
+ // through the set of APICs selected above.
+ uint64_t modOffset = lowestPriorityOffset % apics.size();
+ lowestPriorityOffset++;
+ ApicList::iterator apicIt = apics.begin();
+ while (modOffset--) {
+ apicIt++;
+ assert(apicIt != apics.end());
+ }
+ int selected = *apicIt;
+ apics.clear();
+ apics.push_back(selected);
}
}
intPort->sendMessage(apics, message,
diff -r 6cbdd76b93db -r 2bfd792b1cc0 src/dev/x86/i82094aa.hh
--- a/src/dev/x86/i82094aa.hh Sun Apr 26 02:09:27 2009 -0700
+++ b/src/dev/x86/i82094aa.hh Sun Apr 26 02:09:54 2009 -0700
@@ -77,6 +77,8 @@
uint8_t id;
uint8_t arbId;
+ uint64_t lowestPriorityOffset;
+
static const uint8_t TableSize = 24;
// This implementation is based on version 0x11, but 0x14 avoids having
// to deal with the arbitration and APIC bus guck.
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
