Hi Gabe, [ I wrote this e-mail almost a month and a half ago and I just noticed that it never got sent. I think it is still relevant]
I've started looking at your patch and in particular some of the translation code in the TimingSimpleCPU. I have a couple of comments. 1) You call dcachePort.peerBlockSize() every time you enter this function. That call is probably actually something that you should cache to avoid the extra virtual function call. 2) You split the translation if the address crosses blocks. It seems that it'd be better to check to see if the access crosses pages, not blocks to save the extra work. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
