> This bug happens when both the translation component and the memory > access component finish inline before returning. When that happens, > completeAcc is effectively called from initiateAcc and you get into > trouble. > > The translation component will complete inline in all cases except TLB > misses in X86. It will complete inline in all cases with any other > ISA. Since this bug came up on Alpha, that part of things is > unavoidable right now. > > The second part comes in when the memory access component essentially > doesn't happen. I'm a little fuzzy on the details, but if a store > conditional fails, the CPU can skip talking to the memory access and > go directly to completeDataAccess. > > The overhead my change would add is two writes to a bool and two ifs, > and I would have to imagine that's a lot more lightweight than > creating, initializing, and scheduling a new event for all types of > translation. My change also applies only once to each memory > instruction where some unaligned accesses may be translated in two > chunks. > > We could probably streamline things a little and only check if we're > in initiateAcc on code paths that skip going to memory.
What if you use my change instead? (Get rid of the traceData function parameter and use xc->traceData) Incidentally, there's a bunch of "if (traceData) ..." in the generated code and it's not wrapped with "#if TRACING_ON" Would be nice if that could be changed as part of this too. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
