I don't think I can respond to every point in this discussion, but here are my general thoughts:
- Though they look superficially similar, the SPARC/MIPS single/double FP accesses shouldn't necessarily be handled the same way as x86 partial-register writes. They're both awkward and ugly, but there are different degrees of abomination at play here. - From Gabe's description, I think the "hack" he put in for SPARC is actually the right way to solve the FP register issue. To the extent possible, the source and destination register indices should be sufficient to manage instruction dependences without any extraneous calculation, and his solution of treating the double-register accesses as two registers meets this criterion, while Korey's width attribute does not. - A modern out-of-order CPU implementation is not very likely to allocate single- and double-precision FP regs differently, IMO. It might be interesting to read up on the MIPS R10K (there was a good IEEE Micro article on it many years ago) to see how they treat this. It might require some hacking in the CPU model for these ISAs to know that an instruction with two dest regs really just needs one destination reg. Then again if there are no FP instructions that actually have two destinations then you don't even need to check, just always allocate one and ignore the number of entries in the destRegIdx array. Steve
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