changeset 2d26c346f1be in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=2d26c346f1be
description:
ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower
<d...@cs.wisc.edu>
RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
diffstat:
29 files changed, 1149 insertions(+), 301 deletions(-)
configs/example/ruby.config | 190 ++++++++++++++++
configs/example/ruby_se.py | 172 ++++++++++++++
src/mem/RubyMemory.py | 46 +++
src/mem/SConscript | 4
src/mem/gems_common/ioutil/initvar.hh | 2
src/mem/ruby/common/Driver.hh | 24 --
src/mem/ruby/init.cc | 63 ++++-
src/mem/ruby/init.hh | 4
src/mem/ruby/interfaces/mf_api.hh | 165 --------------
src/mem/ruby/recorder/TraceRecord.cc | 18 +
src/mem/ruby/system/CacheMemory.hh | 13 -
src/mem/ruby/system/Sequencer.cc | 58 +++-
src/mem/ruby/system/Sequencer.hh | 8
src/mem/ruby/system/StoreBuffer.cc | 16 -
src/mem/ruby/system/StoreBuffer.hh | 5
src/mem/ruby/system/System.cc | 79 +++---
src/mem/ruby/system/System.hh | 4
src/mem/ruby/tester/Check.cc | 77 +++++-
src/mem/ruby/tester/DetermGETXGenerator.cc | 11
src/mem/ruby/tester/DetermInvGenerator.cc | 21 +
src/mem/ruby/tester/DetermSeriesGETSGenerator.cc | 11
src/mem/ruby/tester/DeterministicDriver.cc | 15 -
src/mem/ruby/tester/DeterministicDriver.hh | 3
src/mem/ruby/tester/RequestGenerator.cc | 30 ++
src/mem/ruby/tester/SyntheticDriver.cc | 19 -
src/mem/ruby/tester/SyntheticDriver.hh | 2
src/mem/ruby/tester/main.cc | 5
src/mem/rubymem.cc | 256 ++++++++++++++++++++++
src/mem/rubymem.hh | 129 +++++++++++
diffs (truncated from 2046 to 300 lines):
diff -r 29b7b7aba911 -r 2d26c346f1be configs/example/ruby.config
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/example/ruby.config Mon May 11 10:38:46 2009 -0700
@@ -0,0 +1,190 @@
+//Default parameters, taken from
/athitos/export/08spr_ee382a/sanchezd/runs/gen-scripts/ruby.defaults
+
+//General config
+g_DEADLOCK_THRESHOLD: 20000000
+RANDOMIZATION: false
+g_tester_length: 0
+SIMICS_RUBY_MULTIPLIER: 1
+OPAL_RUBY_MULTIPLIER: 1
+TRANSACTION_TRACE_ENABLED: false
+USER_MODE_DATA_ONLY: false
+PROFILE_HOT_LINES: false
+PROFILE_ALL_INSTRUCTIONS: false
+PRINT_INSTRUCTION_TRACE: false
+g_DEBUG_CYCLE: 0
+PERFECT_MEMORY_SYSTEM: false
+PERFECT_MEMORY_SYSTEM_LATENCY: 0
+DATA_BLOCK: false
+
+// Line, page sizes
+g_DATA_BLOCK_BYTES: 64
+g_PAGE_SIZE_BYTES: 8192
+
+
+g_REPLACEMENT_POLICY: PSEDUO_LRU
+// For all caches (sic)
+
+// L1 config
+// 32KB, 4-way SA
+L1_CACHE_ASSOC: 4
+L1_CACHE_NUM_SETS_BITS: 7
+// Single-cycle latency, hits take fastpath
+SEQUENCER_TO_CONTROLLER_LATENCY: 1
+REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
+// L1->L2 delays
+L1_REQUEST_LATENCY: 1
+L1_RESPONSE_LATENCY: 1
+
+// L2 parameters
+// 4 MB, 16-way SA
+L2_CACHE_ASSOC: 16
+L2_CACHE_NUM_SETS_BITS: 12
+MAP_L2BANKS_TO_LOWEST_BITS: false
+// Bank latencies
+L2_RESPONSE_LATENCY: 10
+L2_TAG_LATENCY: 5
+
+
+// Directory latencies
+// The one that counts, we have perfect dirs
+DIRECTORY_CACHE_LATENCY: 6
+// should not be used, but just in case...
+DIRECTORY_LATENCY: 6
+
+// Simple network parameters
+// external links
+NETWORK_LINK_LATENCY: 1
+// intra-chip links
+ON_CHIP_LINK_LATENCY: 1
+
+// General latencies
+RECYCLE_LATENCY: 1
+//Used in MessageBuffer, also MSI_MOSI_CMP dir controller
+
+
+// Unused parameters, good to define them to really weird things just in case
+NULL_LATENCY: 100000
+// Only SMP and token CMP protocols
+ISSUE_LATENCY: 100000
+// Only SMP, example protocols
+CACHE_RESPONSE_LATENCY: 100000
+// Only SMP protocols
+COPY_HEAD_LATENCY: 100000
+// In no protocols or ruby code
+L2_RECYCLE_LATENCY: 100000
+// In no protocols or ruby code
+TIMER_LATENCY: 100000
+// Not used
+TBE_RESPONSE_LATENCY: 100000
+// Not used
+PERIODIC_TIMER_WAKEUPS: false
+// Not used
+BLOCK_STC: false
+// Not used
+SINGLE_ACCESS_L2_BANKS: false
+// Not used
+
+// Main memory latency
+MEMORY_RESPONSE_LATENCY_MINUS_2: 448 //not used in _m, see below
+
+PROFILE_EXCEPTIONS: false
+PROFILE_XACT: false
+PROFILE_NONXACT: true
+XACT_DEBUG: false
+XACT_DEBUG_LEVEL: 1
+XACT_MEMORY: false
+XACT_ENABLE_TOURMALINE: false
+XACT_NUM_CURRENT: 0
+XACT_LAST_UPDATE: 0
+XACT_ISOLATION_CHECK: false
+PERFECT_FILTER: true
+READ_WRITE_FILTER: Perfect_
+PERFECT_VIRTUAL_FILTER: true
+VIRTUAL_READ_WRITE_FILTER: Perfect_
+PERFECT_SUMMARY_FILTER: true
+SUMMARY_READ_WRITE_FILTER: Perfect_
+XACT_EAGER_CD: true
+XACT_LAZY_VM: false
+XACT_CONFLICT_RES: BASE
+XACT_COMMIT_TOKEN_LATENCY: 0
+XACT_NO_BACKOFF: false
+XACT_LOG_BUFFER_SIZE: 0
+XACT_STORE_PREDICTOR_HISTORY: 0
+XACT_STORE_PREDICTOR_ENTRIES: 0
+XACT_STORE_PREDICTOR_THRESHOLD: 0
+XACT_FIRST_ACCESS_COST: 0
+XACT_FIRST_PAGE_ACCESS_COST: 0
+ENABLE_MAGIC_WAITING: false
+ENABLE_WATCHPOINT: false
+XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
+ATMTP_ENABLED: false
+ATMTP_ABORT_ON_NON_XACT_INST: false
+ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
+ATMTP_XACT_MAX_STORES: 0
+ATMTP_DEBUG_LEVEL: 0
+XACT_LENGTH: 0
+XACT_SIZE: 0
+ABORT_RETRY_TIME: 0
+
+
+// Allowed parallelism in controllers
+L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
+L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 1000
+DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 1000
+g_SEQUENCER_OUTSTANDING_REQUESTS: 16
+
+//TBEs == MSHRs (global)
+NUMBER_OF_TBES: 128
+NUMBER_OF_L1_TBES: 32
+// unused in CMP protocols
+NUMBER_OF_L2_TBES: 32
+// unused in CMP protocols
+
+
+// TSO & WBuffer params (unused)
+FINITE_BUFFERING: false
+FINITE_BUFFER_SIZE: 3
+PROCESSOR_BUFFER_SIZE: 10
+PROTOCOL_BUFFER_SIZE: 32
+TSO: false
+
+// General network params
+g_endpoint_bandwidth: 10000
+g_adaptive_routing: true
+NUMBER_OF_VIRTUAL_NETWORKS: 5
+FAN_OUT_DEGREE: 4
+// for HIERARCHICAL_SWITCH
+
+
+// Detailed Memory Controller Params (only used in _m protocols)
+MEM_BUS_CYCLE_MULTIPLIER: 5
+BANKS_PER_RANK: 8
+RANKS_PER_DIMM: 2
+DIMMS_PER_CHANNEL: 2
+BANK_BIT_0: 8
+RANK_BIT_0: 11
+DIMM_BIT_0: 12
+
+BANK_QUEUE_SIZE: 12
+BANK_BUSY_TIME: 22
+RANK_RANK_DELAY: 2
+READ_WRITE_DELAY: 3
+BASIC_BUS_BUSY_TIME: 3
+MEM_CTL_LATENCY: 20
+REFRESH_PERIOD: 3120
+TFAW: 0
+//flip a coin to delay requests by one cycle, introduces non-determinism
+MEM_RANDOM_ARBITRATE: 50
+MEM_FIXED_DELAY: 0
+
+
+//Configuration-specific parameters
+g_NUM_PROCESSORS: 1
+g_NUM_CHIPS: 1
+g_PROCS_PER_CHIP: 1
+g_NUM_L2_BANKS: 1
+g_NUM_MEMORIES: 4
+g_PRINT_TOPOLOGY: true
+g_GARNET_NETWORK: true
+g_DETAIL_NETWORK: true
+g_FLIT_SIZE: 8
diff -r 29b7b7aba911 -r 2d26c346f1be configs/example/ruby_se.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/example/ruby_se.py Mon May 11 10:38:46 2009 -0700
@@ -0,0 +1,172 @@
+# Copyright (c) 2006-2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+# Simple test script
+#
+# "m5 test.py"
+
+import m5
+
+if m5.build_env['FULL_SYSTEM']:
+ m5.panic("This script requires syscall emulation mode (*_SE).")
+
+from m5.objects import *
+import os, optparse, sys
+from os.path import join as joinpath
+m5.AddToPath('../common')
+import Simulation
+#from Caches import *
+from cpu2000 import *
+
+# Get paths we might need. It's expected this file is in m5/configs/example.
+config_path = os.path.dirname(os.path.abspath(__file__))
+config_root = os.path.dirname(config_path)
+m5_root = os.path.dirname(config_root)
+
+parser = optparse.OptionParser()
+
+# Benchmark options
+parser.add_option("-c", "--cmd",
+ default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
+ help="The binary to run in syscall emulation mode.")
+parser.add_option("-o", "--options", default="",
+ help='The options to pass to the binary, use " " around the entire string')
+parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
+parser.add_option("--output", default="", help="Redirect stdout to a file.")
+parser.add_option("--errout", default="", help="Redirect stderr to a file.")
+parser.add_option("--ruby-debug", action="store_true")
+parser.add_option("--ruby-debug-file", default="", help="Ruby debug out file
(stdout if blank)")
+
+execfile(os.path.join(config_root, "common", "Options.py"))
+
+(options, args) = parser.parse_args()
+
+if args:
+ print "Error: script doesn't take any positional arguments"
+ sys.exit(1)
+
+if options.bench:
+ try:
+ if m5.build_env['TARGET_ISA'] != 'alpha':
+ print >>sys.stderr, "Simpoints code only works for Alpha ISA at
this time"
+ sys.exit(1)
+ exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
+ process = workload.makeLiveProcess()
+ except:
+ print >>sys.stderr, "Unable to find workload for %s" % options.bench
+ sys.exit(1)
+else:
+ process = LiveProcess()
+ process.executable = options.cmd
+ process.cmd = [options.cmd] + options.options.split()
+
+
+if options.input != "":
+ process.input = options.input
+if options.output != "":
+ process.output = options.output
+if options.errout != "":
+ process.errout = options.errout
+
+if options.detailed:
+ #check for SMT workload
+ workloads = options.cmd.split(';')
+ if len(workloads) > 1:
+ process = []
+ smt_idx = 0
+ inputs = []
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
