changeset 4ace94e801cb in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=4ace94e801cb description: SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
diffstat: 1 file changed, 2 insertions(+), 2 deletions(-) src/arch/sparc/nativetrace.cc | 4 ++-- diffs (21 lines): diff -r 70172be3f986 -r 4ace94e801cb src/arch/sparc/nativetrace.cc --- a/src/arch/sparc/nativetrace.cc Sat Jul 25 00:50:27 2009 -0400 +++ b/src/arch/sparc/nativetrace.cc Sat Jul 25 15:14:00 2009 -0700 @@ -36,7 +36,7 @@ namespace Trace { -static char *intRegNames[SparcISA::NumIntArchRegs] = { +static const char *intRegNames[SparcISA::NumIntArchRegs] = { //Global registers "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", //Output registers @@ -58,7 +58,7 @@ // I doubt a real SPARC will describe more integer registers than this. assert(SparcISA::NumIntArchRegs == 32); - char **regName = intRegNames; + const char **regName = intRegNames; for (int i = 0; i < SparcISA::NumIntArchRegs; i++) { regVal = tc->readIntReg(i); read(&realRegVal, sizeof(realRegVal)); _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev