changeset 7ed8937e375a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7ed8937e375a
description:
Fix setting of INST_FETCH flag for O3 CPU.
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
diffstat:
6 files changed, 17 insertions(+), 21 deletions(-)
src/cpu/base_dyn_inst.hh | 10 ++++------
src/cpu/o3/fetch_impl.hh | 6 +++---
src/cpu/ozone/inorder_back_end.hh | 4 ----
src/cpu/simple/base.cc | 1 -
src/mem/cache/cache_impl.hh | 5 +++--
src/mem/physical.cc | 12 +++++++-----
diffs (151 lines):
diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Sat Aug 01 22:50:13 2009 -0700
+++ b/src/cpu/base_dyn_inst.hh Sat Aug 01 22:50:14 2009 -0700
@@ -857,9 +857,8 @@
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->contextId(), threadNumber);
+ Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
+ thread->contextId(), threadNumber);
fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
@@ -913,9 +912,8 @@
}
reqMade = true;
- Request *req = new Request();
- req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->contextId(), threadNumber);
+ Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
+ thread->contextId(), threadNumber);
fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat Aug 01 22:50:13 2009 -0700
+++ b/src/cpu/o3/fetch_impl.hh Sat Aug 01 22:50:14 2009 -0700
@@ -596,9 +596,9 @@
// Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
// Build request here.
- RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
- fetch_PC, cpu->thread[tid]->contextId(),
- tid);
+ RequestPtr mem_req =
+ new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
+ fetch_PC, cpu->thread[tid]->contextId(), tid);
memReq[tid] = mem_req;
diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/ozone/inorder_back_end.hh
--- a/src/cpu/ozone/inorder_back_end.hh Sat Aug 01 22:50:13 2009 -0700
+++ b/src/cpu/ozone/inorder_back_end.hh Sat Aug 01 22:50:14 2009 -0700
@@ -211,7 +211,6 @@
memReq->cmd = Read;
memReq->completionEvent = NULL;
memReq->time = curTick;
- memReq->flags &= ~INST_FETCH;
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
@@ -252,7 +251,6 @@
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
- memReq->flags &= ~INST_FETCH;
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
@@ -293,7 +291,6 @@
req->time = curTick;
assert(!req->data);
req->data = new uint8_t[64];
- req->flags &= ~INST_FETCH;
Fault fault = cpu->read(req, data);
memcpy(req->data, &data, sizeof(T));
@@ -363,7 +360,6 @@
memcpy(req->data,(uint8_t *)&data,req->size);
req->completionEvent = NULL;
req->time = curTick;
- req->flags &= ~INST_FETCH;
MemAccessResult result = dcacheInterface->access(req);
// Ugly hack to get an event scheduled *only* if the access is
diff -r 9e35cdc95e81 -r 7ed8937e375a src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc Sat Aug 01 22:50:13 2009 -0700
+++ b/src/cpu/simple/base.cc Sat Aug 01 22:50:14 2009 -0700
@@ -282,7 +282,6 @@
memReq->dest = dest_addr;
memReq->size = 64;
memReq->time = curTick;
- memReq->flags &= ~INST_FETCH;
dcacheInterface->access(memReq);
}
}
diff -r 9e35cdc95e81 -r 7ed8937e375a src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Sat Aug 01 22:50:13 2009 -0700
+++ b/src/mem/cache/cache_impl.hh Sat Aug 01 22:50:14 2009 -0700
@@ -268,8 +268,9 @@
blk = tags->accessBlock(pkt->getAddr(), lat);
- DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
- (blk) ? "hit" : "miss");
+ DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
+ pkt->req->isInstFetch() ? " (ifetch)" : "",
+ pkt->getAddr(), (blk) ? "hit" : "miss");
if (blk != NULL) {
diff -r 9e35cdc95e81 -r 7ed8937e375a src/mem/physical.cc
--- a/src/mem/physical.cc Sat Aug 01 22:50:13 2009 -0700
+++ b/src/mem/physical.cc Sat Aug 01 22:50:14 2009 -0700
@@ -211,8 +211,8 @@
#define CASE(A, T) \
case sizeof(T): \
- DPRINTF(MemoryAccess, A " of size %i on address 0x%x data 0x%x\n", \
- pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \
+ DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n", \
+ A, pkt->getSize(), pkt->getAddr(), pkt->get<T>()); \
break
@@ -224,8 +224,8 @@
CASE(A, uint16_t); \
CASE(A, uint8_t); \
default: \
- DPRINTF(MemoryAccess, A " of size %i on address 0x%x\n", \
- pkt->getSize(), pkt->getAddr()); \
+ DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n", \
+ A, pkt->getSize(), pkt->getAddr()); \
} \
} while (0)
@@ -281,6 +281,7 @@
if (overwrite_mem)
std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
+ assert(!pkt->req->isInstFetch());
TRACE_PACKET("Read/Write");
} else if (pkt->isRead()) {
assert(!pkt->isWrite());
@@ -289,11 +290,12 @@
}
if (pmemAddr)
memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
- TRACE_PACKET("Read");
+ TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
} else if (pkt->isWrite()) {
if (writeOK(pkt)) {
if (pmemAddr)
memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
+ assert(!pkt->req->isInstFetch());
TRACE_PACKET("Write");
}
} else if (pkt->isInvalidate()) {
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