Before we worry about the details of this patch, I have a higher-level
question: why do we need a separate DMA request type and port at all?
On the M5 side, we've gotten by just fine so far with ReadReq and
WriteReq, and M5 devices don't explicitly mark their DMA requests as
such.  I understand that that's how Ruby does things, but I think we
should discuss whether that's the right thing for Ruby to be doing
before we move ahead with exposing it in the port/request interface.
If we need to manage it temporarily as a transition thing then there
might be less invasive ways of doing it.

Polina, the fixes you have to src/cpu/memtest/SConscript are needed
and are independent of DMA testing, so please commit and push just
that file as a separate changeset.  (Since it is unrelated, I would
suggest committing it separately even if we were going to go ahead
with the DMA changes.)

Also, on a minor note: I don't know that we have a rule about this,
but I'm generally opposed to putting names or initials in comments,
since (1) these accumulate over time and clutter the comments and (2)
the source code control system makes it relatively easy to figure out
who to blame for a particular change (e.g., 'hg annotate').

Thanks,

Steve

On Tue, Sep 1, 2009 at 7:43 AM, Polina Dudnik<pdud...@gmail.com> wrote:
> Hi,
>
> I am attaching a patch that allows memtest.cc to issue DMA requests.
>
> The changes include:
>
> 1. Add bool use_dma and percent_dma to MemTest.py
> 2. Fix if O3CPU SCons issue that Somayeh had
> 3. Add percent_dma and use_dma to memtest.hh and memtest.cc
> 4. Added generation of dma requests to memtest.cc
> 5. Add DMA_REQUEST flag to request.hh
> 6. Replaced assert with return -1 if DMASequencer is bucy
> 7. Added DMA port in rubymem.cc
> 8. Added DMA request handling in rubymem.cc
>
> Polina
>
> _______________________________________________
> m5-dev mailing list
> m5-dev@m5sim.org
> http://m5sim.org/mailman/listinfo/m5-dev
>
>
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