Never mind. I realized what was going on as I was getting ready for work this morning. imm is the same size for all microops, but when it's stored internal to the microop it gets truncated into a 16 bit immediate value. A better solution might be to make the wripi instruction sign extend its immediate since a signed displacement sounds like it would be a lot more common. If you'd like to give that a try, the code you want is in regop.isa. I'll try that this evening if I have time. If that works for you please let me know.
Gabe Quoting Gabe Black <[email protected]>: > You're patch may make your regression pass, but I don't think it quite > fixes the real issue. The immediate value should be read in as 1 byte > (as encoded in predecoder_tables.cc) and then sign extended to 64 bits > (predecoder.cc). That's the value that ends up in "imm" effectively. I > don't know why moving that same value into a register would behave any > differently than using it directly in wripi since imm is provided to > each microop in parallel at decode time. It could be that by changing > the value of t2, you're affecting some later instruction that uses it > uninitialized, and that would be worse. If you could send me a trace of > this instruction behaving badly and a few instructions around it with > the Exec, Predecoder, and IntRegs trace flags turned on, it might help > identify what's not working. It's quite likely there's a bug here, but I > want to make sure we fix it rather than just getting around it. > > Gabe > > Vince Weaver wrote: >> Hello >> >> the "loop" instructions on x86 are broken, they seem to be using a >> 16-bit immediate for the offset instead of the proper signed 8-bit one. >> This very obviously breaks instructions trying to loop backward. >> >> The patch below fixes things on my regression test, though I might have >> something wrong (the uop routines are a bit hard to follow). Also the >> other two LOOP variations probably need the fix too. >> >> This allows the x86 version of my regression test run properly >> ( http://deater.net/weave/vmwprod/asm/ll/qemu_tests.html ) >> >> Vince >> >> diff -r 3b2d7fdff6b1 >> src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py >> --- >> a/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py Fri Sep >> >> 11 16:19:31 2009 -0500 >> +++ >> b/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py Mon Sep >> >> 14 22:51:52 2009 -0400 >> @@ -56,8 +56,9 @@ >> microcode = ''' >> def macroop LOOP_I { >> rdip t1 >> + limm t2, imm, dataSize=8 >> subi rcx, rcx, 1, flags=(EZF,), dataSize=asz >> - wripi t1, imm, flags=(nCEZF,) >> + wrip t1, t2, flags=(nCEZF,) >> }; >> >> def macroop LOOPNE_I { >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
