# HG changeset patch # User Timothy M. Jones <tjon...@inf.ed.ac.uk> # Date 1255513122 -3600 # Node ID 3208f4cd352d269437802d372b7acf873a4a64db # Parent a485937b7038f1616d37a28b242b8a6fbdeb068c Alter the miscregs from control to integer registers.
This enables them to be renamed in O3CPU. diff --git a/src/arch/powerpc/insts/branch.cc b/src/arch/powerpc/insts/branch.cc --- a/src/arch/powerpc/insts/branch.cc +++ b/src/arch/powerpc/insts/branch.cc @@ -151,8 +151,7 @@ Addr BranchRegCond::branchTarget(ThreadContext *tc) const { - uint32_t regVal = - tc->readMiscReg(_srcRegIdx[_numSrcRegs - 1] - Ctrl_Base_DepTag); + uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); return (regVal & 0xfffffffc); } diff --git a/src/arch/powerpc/isa/operands.isa b/src/arch/powerpc/isa/operands.isa --- a/src/arch/powerpc/isa/operands.isa +++ b/src/arch/powerpc/isa/operands.isa @@ -63,16 +63,18 @@ 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9), # Control registers - 'CR': ('ControlReg', 'uw', 0, 'IsInteger', 9), - 'LR': ('ControlReg', 'uw', 1, 'IsInteger', 9), - 'CTR': ('ControlReg', 'uw', 2, 'IsInteger', 9), - 'XER': ('ControlReg', 'uw', 3, 'IsInteger', 9), - 'FPSCR': ('ControlReg', 'uw', 4, 'IsFloating', 9), + 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), + 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), + 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9), + 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9), + + # Setting as IntReg so things are stored as an integer, not double + 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), # Registers for linked loads and stores - 'Rsv': ('ControlReg', 'uw', 5, 'IsInteger', 9), - 'RsvLen': ('ControlReg', 'uw', 6, 'IsInteger', 9), - 'RsvAddr': ('ControlReg', 'uw', 7, 'IsInteger', 9), + 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9), + 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9), + 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9), # Hack for non-full-system syscall emulation 'R0': ('IntReg', 'uw', '0', None, 1), diff --git a/src/arch/powerpc/miscregs.hh b/src/arch/powerpc/miscregs.hh --- a/src/arch/powerpc/miscregs.hh +++ b/src/arch/powerpc/miscregs.hh @@ -37,24 +37,10 @@ { enum MiscRegIndex { - MISCREG_CR = 0, - MISCREG_XER, - MISCREG_LR, - MISCREG_CTR, - MISCREG_RSV, - MISCREG_RSV_LEN, - MISCREG_RSV_ADDR, - MISCREG_FPSCR, - NUM_MISCREGS + NUM_MISCREGS = 0 }; const char * const miscRegName[NUM_MISCREGS] = { - "cr", - "xer", - "lr", - "ctr", - "rsv", "rsv-len", "rsv-addr", - "fpscr" }; BitUnion32(Cr) diff --git a/src/arch/powerpc/registers.hh b/src/arch/powerpc/registers.hh --- a/src/arch/powerpc/registers.hh +++ b/src/arch/powerpc/registers.hh @@ -46,20 +46,20 @@ // Floating point register file entry type typedef uint64_t FloatRegBits; typedef double FloatReg; - -// FPSCR and other registers typedef uint64_t MiscReg; // Constants Related to the number of registers const int NumIntArchRegs = 32; -const int NumIntSpecialRegs = 1; // The zero register + +// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR +// and zero register, which doesn't actually exist but needs a number +const int NumIntSpecialRegs = 9; const int NumFloatArchRegs = 32; const int NumFloatSpecialRegs = 0; const int NumInternalProcRegs = 0; const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; - const int NumMiscRegs = NUM_MISCREGS; // Semantically meaningful register indices @@ -73,7 +73,7 @@ const int StackPointerReg = 1; // There isn't one in PowerPC, but we need to define one somewhere -const int ZeroReg = NumIntArchRegs; +const int ZeroReg = NumIntRegs - 1; const int SyscallNumReg = 0; const int SyscallPseudoReturnReg = 3; @@ -90,13 +90,14 @@ } AnyReg; enum MiscIntRegNums { - cr, - xer, - lr, - ctr, - rsv, - rsv_len, - rsv_addr + INTREG_CR = NumIntArchRegs, + INTREG_XER, + INTREG_LR, + INTREG_CTR, + INTREG_FPSCR, + INTREG_RSV, + INTREG_RSV_LEN, + INTREG_RSV_ADDR }; } // PowerpcISA namespace -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev