> The Power ISA book states that instructions must be word aligned. All > other accesses can be unaligned. I.e. there are no alignment restrictions > at all for loads and stores. This is now causing me problems in the cache > when I try to do an unaligned store that crosses a block boundary. I've > looked at other ISAs but they don't seem to have the same problems. x86 will.
> I'm thinking that the fix should be to split the store (or load) into two > memory requests, one for each of the cache lines to access. My question is > - where is the best place to do this? In LSQUnit::insertStore would be the > easiest place, but is that the correct place for it? However, since this > is Power specific, maybe it should be handled within the code for this ISA > only? Any thoughts on this would be much appreciated before I go hacking > away through the code. It would be really nice if you didn't do it in the ISA since x86 also allows unaligned operations. It may be nice for you and Gabe (and Steve?) to hash things out a little bit before you dive in. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
