changeset 0e5037cecaf7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=0e5037cecaf7
description:
X86: Add support for x86 psrldq and pslldq instructions
These are complicated instructions and the micro-code might be
suboptimal.
This has been tested with some small sample programs (attached)
The psrldq instruction is needed by various spec2k programs.
diffstat:
3 files changed, 78 insertions(+), 4 deletions(-)
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 -
src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py | 40
+++++++++-
src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py | 38
+++++++++
diffs (109 lines):
diff -r ea20065f6614 -r 0e5037cecaf7
src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Fri Oct 30 15:52:33
2009 -0400
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Fri Oct 30 12:49:37
2009 -0400
@@ -673,9 +673,9 @@
//0x3: group14_pshimq();
0x3: decode MODRM_REG {
0x2: PSRLQ(VRo,Ib);
- 0x3: WarnUnimpl::psrldq_VRo_Ib();
+ 0x3: PSRLDQ(VRo,Ib);
0x6: PSLLQ(VRo,Ib);
- 0x7: WarnUnimpl::pslldq_VRo_Ib();
+ 0x7: PSLLDQ(VRo,Ib);
default: UD2();
}
0x4: PCMPEQB(Vo,Wo);
diff -r ea20065f6614 -r 0e5037cecaf7
src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
--- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
Fri Oct 30 15:52:33 2009 -0400
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
Fri Oct 30 12:49:37 2009 -0400
@@ -122,5 +122,43 @@
mslli xmml, xmml, imm, size=8, ext=0
mslli xmmh, xmmh, imm, size=8, ext=0
};
+
+def macroop PSLLDQ_XMM_I {
+
+ limm t2, 8
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("pslldq_less_8"), flags=(nCECF,)
+
+ # Greater than 8
+
+ limm t2, 16
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("pslldq_less_16"), flags=(nCECF,)
+
+ # Greater than 16
+
+ lfpimm xmml, 0
+ lfpimm xmmh, 0
+ br label("pslldq_end")
+
+pslldq_less_16:
+
+ # Between 8 and 16
+
+ mslli xmmh, xmml, "(IMMEDIATE-8)<<3", size=8, ext=0
+ lfpimm xmml, 0
+ br label("pslldq_end")
+
+pslldq_less_8:
+
+ # Less than 8
+
+ msrli ufp1, xmml, "(8-IMMEDIATE) << 3", size=8, ext=0
+ mslli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+ mslli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+ mor xmmh, xmmh, ufp1
+
+pslldq_end:
+ fault "NoFault"
+};
'''
-# PSLLDQ
diff -r ea20065f6614 -r 0e5037cecaf7
src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
--- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
Fri Oct 30 15:52:33 2009 -0400
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
Fri Oct 30 12:49:37 2009 -0400
@@ -122,5 +122,41 @@
msrli xmml, xmml, imm, size=8, ext=0
msrli xmmh, xmmh, imm, size=8, ext=0
};
+
+def macroop PSRLDQ_XMM_I {
+ limm t2, 8
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("psrldq_less_8"), flags=(nCECF,)
+ # Greater than 8
+
+ limm t2, 16
+ subi t1, t2, imm, flags=(ECF,), dataSize=1
+ br label("psrldq_less_16"), flags=(nCECF,)
+
+ # Greater than 16
+
+ lfpimm xmml, 0
+ lfpimm xmmh, 0
+ br label("psrldq_end")
+
+psrldq_less_16:
+
+ # Between 8 and 16
+
+ msrli xmml, xmmh, "(IMMEDIATE-8)<<3", size=8, ext=0
+ lfpimm xmmh, 0
+ br label("psrldq_end")
+
+psrldq_less_8:
+
+ # Less than 8
+
+ mslli ufp1, xmmh, "(8-IMMEDIATE) << 3", size=8, ext=0
+ msrli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+ msrli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+ mor xmml, xmml, ufp1
+
+psrldq_end:
+ fault "NoFault"
+};
'''
-# PSRLDQ
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