changeset 451ddd5d50d6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=451ddd5d50d6
description:
MIPS: Update stats for updated initial environment.
diffstat:
12 files changed, 582 insertions(+), 590 deletions(-)
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini | 5
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 12
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 286 ++--
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini | 5
tests/quick/00.hello/ref/mips/linux/o3-timing/simout | 12
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt | 579 +++++-----
tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini | 2
tests/quick/00.hello/ref/mips/linux/simple-atomic/simout | 12
tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt | 20
tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini | 5
tests/quick/00.hello/ref/mips/linux/simple-timing/simout | 12
tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt | 222 +--
diffs (truncated from 1677 to 300 lines):
diff -r f130ea67e453 -r 451ddd5d50d6
tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini Thu Dec
31 15:30:51 2009 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini Thu Dec
31 15:30:51 2009 -0500
@@ -132,7 +132,6 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -167,7 +166,6 @@
latency=1000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -202,7 +200,6 @@
latency=10000
max_miss_count=0
mshrs=10
-prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
@@ -244,7 +241,7 @@
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff -r f130ea67e453 -r 451ddd5d50d6
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Thu Dec 31
15:30:51 2009 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout Thu Dec 31
15:30:51 2009 -0500
@@ -5,13 +5,13 @@
All Rights Reserved
-M5 compiled Sep 24 2009 12:19:09
-M5 revision 9bc3e4611009+ 6661+ default tip
-M5 started Sep 24 2009 12:19:46
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d
build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re
tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
+M5 compiled Dec 29 2009 23:25:57
+M5 revision b49d467587f8 6811 default processinit.patch qtip tip
+M5 started Dec 29 2009 23:25:59
+M5 executing on fajita
+command line: build/MIPS_SE/m5.opt -d
build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re
tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 29521500 because target called exit()
+Exiting @ tick 29940500 because target called exit()
diff -r f130ea67e453 -r 451ddd5d50d6
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt Thu Dec
31 15:30:51 2009 -0500
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt Thu Dec
31 15:30:51 2009 -0500
@@ -1,99 +1,99 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 29581 #
Simulator instruction rate (inst/s)
-host_mem_usage 155804 #
Number of bytes of host memory used
-host_seconds 0.19 #
Real time elapsed on the host
-host_tick_rate 153369596 #
Simulator tick rate (ticks/s)
+host_inst_rate 2950 #
Simulator instruction rate (inst/s)
+host_mem_usage 204636 #
Number of bytes of host memory used
+host_seconds 1.98 #
Real time elapsed on the host
+host_tick_rate 15157943 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 5685 #
Number of instructions simulated
+sim_insts 5827 #
Number of instructions simulated
sim_seconds 0.000030 #
Number of seconds simulated
-sim_ticks 29521500 #
Number of ticks simulated
-system.cpu.AGEN-Unit.instReqsProcessed 2058 #
Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.instReqsProcessed 5686
# Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.predictedNotTaken 789
# Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 96
# Number of Branches Predicted As Taken (True).
-system.cpu.Decode-Unit.instReqsProcessed 5686 #
Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.instReqsProcessed 3624
# Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 516
# Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect 34
# Number of Branches Incorrectly Predicted As Taken.
+sim_ticks 29940500 #
Number of ticks simulated
+system.cpu.AGEN-Unit.instReqsProcessed 2090 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.instReqsProcessed 5828
# Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.predictedNotTaken 826
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 90
# Number of Branches Predicted As Taken (True).
+system.cpu.Decode-Unit.instReqsProcessed 5828 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.instReqsProcessed 3734
# Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 541
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 35
# Number of Branches Incorrectly Predicted As Taken.
system.cpu.Fetch-Buffer-T0.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T0.instsBypassed 0 #
Number of Instructions Bypassed.
system.cpu.Fetch-Buffer-T1.instReqsProcessed 0
# Number of Instructions Requests that completed in this resource.
system.cpu.Fetch-Buffer-T1.instsBypassed 0 #
Number of Instructions Bypassed.
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 11373
# Number of Instructions Requests that completed in this resource.
-system.cpu.Graduation-Unit.instReqsProcessed 5685
# Number of Instructions Requests that completed in this resource.
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 11657
# Number of Instructions Requests that completed in this resource.
+system.cpu.Graduation-Unit.instReqsProcessed 5827
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 1
# Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 8
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 3
# Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 10479
# Number of Instructions Requests that completed in this resource.
-system.cpu.committedInsts 5685 #
Number of Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 5685 #
Number of Instructions Simulated (Total)
-system.cpu.cpi 10.385928 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 10.385928 #
CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1134 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 56207.317073
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53207.317073
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1052 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4609000 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.072310 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 82 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4363000
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.072310 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 82 #
number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 924 #
number of WriteReq accesses(hits+misses)
+system.cpu.RegFile-Manager.instReqsProcessed 10713
# Number of Instructions Requests that completed in this resource.
+system.cpu.committedInsts 5827 #
Number of Instructions Simulated (Per-Thread)
+system.cpu.committedInsts_total 5827 #
Number of Instructions Simulated (Total)
+system.cpu.cpi 10.276643 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 10.276643 #
CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1165 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 56201.149425
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53201.149425
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1078 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4889500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.074678 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 87 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 4628500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.074678 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 87 #
number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 925 #
number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500
# average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 860 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_hits 861 #
number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 3619500 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069264 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate 0.069189 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 64 #
number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 3427500
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 64 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.590909 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.144928 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 2058 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56359.589041 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53359.589041
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 1912 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8228500 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.070943 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 146 #
number of demand (read+write) misses
+system.cpu.dcache.demand_accesses 2090 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 56350.993377 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53350.993377
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 1939 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 8509000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.072249 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 151 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7790500
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.070943 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 146 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 8056000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072249 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 151 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2058 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56359.589041
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53359.589041
# average overall mshr miss latency
+system.cpu.dcache.overall_accesses 2090 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 56350.993377
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53350.993377
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1912 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 8228500 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.070943 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 146 #
number of overall misses
+system.cpu.dcache.overall_hits 1939 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 8509000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.072249 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 151 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7790500
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.070943 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 146 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 8056000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072249 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 151 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 #
number of replacements
-system.cpu.dcache.sampled_refs 132 #
Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 84.209307 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 1926 #
Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 88.212490 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 1952 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 #
number of writebacks
-system.cpu.dcache_port.instReqsProcessed 2057 #
Number of Instructions Requests that completed in this resource.
+system.cpu.dcache_port.instReqsProcessed 2089 #
Number of Instructions Requests that completed in this resource.
system.cpu.dtb.accesses 0 #
DTB accesses
system.cpu.dtb.hits 0 #
DTB hits
system.cpu.dtb.misses 0 #
DTB misses
@@ -103,62 +103,62 @@
system.cpu.dtb.write_accesses 0 #
DTB write accesses
system.cpu.dtb.write_hits 0 #
DTB write hits
system.cpu.dtb.write_misses 0 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 5687 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55773.026316
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52773.026316
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5383 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16955000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.053455 #
miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 304 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 16043000
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.053455 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 304 #
number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 5829 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55765.676568
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52765.676568
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5526 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16897000 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.051981 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 15988000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 17.707237 #
Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.237624 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 5687 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55773.026316 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52773.026316
# average overall mshr miss latency
-system.cpu.icache.demand_hits 5383 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16955000 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.053455 #
miss rate for demand accesses
-system.cpu.icache.demand_misses 304 #
number of demand (read+write) misses
+system.cpu.icache.demand_accesses 5829 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55765.676568 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52765.676568
# average overall mshr miss latency
+system.cpu.icache.demand_hits 5526 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16897000 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.051981 #
miss rate for demand accesses
+system.cpu.icache.demand_misses 303 #
number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 16043000
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.053455 #
mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 304 #
number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency 15988000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.051981 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 5687 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55773.026316
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52773.026316
# average overall mshr miss latency
+system.cpu.icache.overall_accesses 5829 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55765.676568
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52765.676568
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5383 #
number of overall hits
-system.cpu.icache.overall_miss_latency 16955000 #
number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.053455 #
miss rate for overall accesses
-system.cpu.icache.overall_misses 304 #
number of overall misses
+system.cpu.icache.overall_hits 5526 #
number of overall hits
+system.cpu.icache.overall_miss_latency 16897000 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.051981 #
miss rate for overall accesses
+system.cpu.icache.overall_misses 303 #
number of overall misses
system.cpu.icache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 16043000
# number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.053455 #
mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 304 #
number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency 15988000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.051981 #
mshr miss rate for overall accesses
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