# HG changeset patch # User Brad Beckmann <brad.beckm...@amd.com> # Date 1263536244 28800 # Node ID fa362ac18a7a7c2f737fc092f987d94f1beb906a # Parent a7113be39b6a4f7ec2398fd87518f49445b1e83f ruby: Added the cache profiler to the new config system
diff -r a7113be39b6a -r fa362ac18a7a configs/example/memtest-ruby.py --- a/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800 +++ b/configs/example/memtest-ruby.py Thu Jan 14 22:17:24 2010 -0800 @@ -115,10 +115,14 @@ # Eventually this code should go in a python file specific to the # MOESI_hammer protocol # - - l1i_cache = L1Cache() - l1d_cache = L1Cache() - l2_cache = L2Cache() + l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i)) + l1i_cache = L1Cache(cache_profiler = l1i_profiler) + + l1d_profiler = CacheProfiler(description = ("l1d_%s_profiler" % i)) + l1d_cache = L1Cache(cache_profiler = l1d_profiler) + + l2_profiler = CacheProfiler(description = ("l2_%s_profiler" % i)) + l2_cache = L2Cache(cache_profiler = l2_profiler) cpu_seq = RubySequencer(icache = l1i_cache, dcache = l1d_cache, diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/CacheProfiler.cc --- a/src/mem/ruby/profiler/CacheProfiler.cc Thu Jan 14 22:17:24 2010 -0800 +++ b/src/mem/ruby/profiler/CacheProfiler.cc Thu Jan 14 22:17:24 2010 -0800 @@ -43,10 +43,10 @@ #include "mem/ruby/profiler/Profiler.hh" #include "mem/gems_common/Vector.hh" -CacheProfiler::CacheProfiler(string description) - : m_requestSize(-1) +CacheProfiler::CacheProfiler(const CacheProfilerParams* params) + : SimObject(params), m_requestSize(-1) { - m_description = description; + m_description = params->description; m_requestTypeVec_ptr = new Vector<int>; m_requestTypeVec_ptr->setSize(int(CacheRequestType_NUM)); @@ -141,3 +141,8 @@ } } +CacheProfiler * +CacheProfilerParams::create() +{ + return new CacheProfiler(this); +} diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/CacheProfiler.hh --- a/src/mem/ruby/profiler/CacheProfiler.hh Thu Jan 14 22:17:24 2010 -0800 +++ b/src/mem/ruby/profiler/CacheProfiler.hh Thu Jan 14 22:17:24 2010 -0800 @@ -46,12 +46,15 @@ #include "mem/protocol/PrefetchBit.hh" #include "mem/protocol/CacheRequestType.hh" +#include "params/CacheProfiler.hh" + template <class TYPE> class Vector; -class CacheProfiler { +class CacheProfiler : public SimObject { public: // Constructors - CacheProfiler(string description); + typedef CacheProfilerParams Params; + CacheProfiler(const Params *); // Destructor ~CacheProfiler(); diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/profiler/Profiler.py --- a/src/mem/ruby/profiler/Profiler.py Thu Jan 14 22:17:24 2010 -0800 +++ b/src/mem/ruby/profiler/Profiler.py Thu Jan 14 22:17:24 2010 -0800 @@ -6,3 +6,8 @@ cxx_class = 'Profiler' hot_lines = Param.Bool(False, "") all_instructions = Param.Bool(False, "") + +class CacheProfiler(SimObject): + type = 'CacheProfiler' + cxx_class = 'CacheProfiler' + description = Param.String("") diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/system/Cache.py --- a/src/mem/ruby/system/Cache.py Thu Jan 14 22:17:24 2010 -0800 +++ b/src/mem/ruby/system/Cache.py Thu Jan 14 22:17:24 2010 -0800 @@ -9,3 +9,4 @@ latency = Param.Int(""); assoc = Param.Int(""); replacement_policy = Param.String("PSEUDO_LRU", ""); + cache_profiler = Param.CacheProfiler(""); diff -r a7113be39b6a -r fa362ac18a7a src/mem/ruby/system/CacheMemory.cc --- a/src/mem/ruby/system/CacheMemory.cc Thu Jan 14 22:17:24 2010 -0800 +++ b/src/mem/ruby/system/CacheMemory.cc Thu Jan 14 22:17:24 2010 -0800 @@ -58,6 +58,7 @@ m_latency = p->latency; m_cache_assoc = p->assoc; m_policy = p->replacement_policy; + m_profiler_ptr = p->cache_profiler; } @@ -363,7 +364,7 @@ void CacheMemory::profileMiss(const CacheMsg & msg) { m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), - msg.getSize(), msg.getPrefetch()); + msg.getSize(), msg.getPrefetch()); } void CacheMemory::recordCacheContents(CacheRecorder& tr) const _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev