--- Begin Message ---
changeset 5aec45d0fc24 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5aec45d0fc24
description:
cache: make tags->insertBlock() and tags->accessBlock() context aware
so that the cache can make context-specific decisions within their various tag
policy implementations.
diffstat:
7 files changed, 18 insertions(+), 15 deletions(-)
src/mem/cache/cache_impl.hh | 9 ++++++---
src/mem/cache/tags/fa_lru.cc | 4 ++--
src/mem/cache/tags/fa_lru.hh | 4 ++--
src/mem/cache/tags/iic.cc | 4 ++--
src/mem/cache/tags/iic.hh | 4 ++--
src/mem/cache/tags/lru.cc | 4 ++--
src/mem/cache/tags/lru.hh | 4 ++--
diffs (159 lines):
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/cache_impl.hh Tue Jan 12 10:53:02 2010 -0800
@@ -266,7 +266,8 @@
return false;
}
- blk = tags->accessBlock(pkt->getAddr(), lat);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ blk = tags->accessBlock(pkt->getAddr(), lat, id);
DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
pkt->req->isInstFetch() ? " (ifetch)" : "",
@@ -299,7 +300,8 @@
incMissCount(pkt);
return false;
}
- tags->insertBlock(pkt->getAddr(), blk);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ tags->insertBlock(pkt->getAddr(), blk, id);
blk->status = BlkValid | BlkReadable;
}
std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
@@ -976,7 +978,8 @@
tempBlock->tag = tags->extractTag(addr);
DPRINTF(Cache, "using temp block for %x\n", addr);
} else {
- tags->insertBlock(addr, blk);
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ tags->insertBlock(pkt->getAddr(), blk, id);
}
} else {
// existing block... probably an upgrade
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/fa_lru.cc
--- a/src/mem/cache/tags/fa_lru.cc Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/fa_lru.cc Tue Jan 12 10:53:02 2010 -0800
@@ -154,7 +154,7 @@
}
FALRUBlk*
-FALRU::accessBlock(Addr addr, int &lat, int *inCache)
+FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache)
{
accesses++;
int tmp_in_cache = 0;
@@ -228,7 +228,7 @@
}
void
-FALRU::insertBlock(Addr addr, FALRU::BlkType *blk)
+FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src)
{
}
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/fa_lru.hh
--- a/src/mem/cache/tags/fa_lru.hh Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/fa_lru.hh Tue Jan 12 10:53:02 2010 -0800
@@ -182,7 +182,7 @@
* @param inCache The FALRUBlk::inCache flags.
* @return Pointer to the cache block.
*/
- FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0);
+ FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache =
0);
/**
* Find the block in the cache, do not update the replacement data.
@@ -200,7 +200,7 @@
*/
FALRUBlk* findVictim(Addr addr, PacketList & writebacks);
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Return the hit latency of this cache.
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/iic.cc
--- a/src/mem/cache/tags/iic.cc Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/iic.cc Tue Jan 12 10:53:02 2010 -0800
@@ -219,7 +219,7 @@
IICTag*
-IIC::accessBlock(Addr addr, int &lat)
+IIC::accessBlock(Addr addr, int &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = hash(addr);
@@ -338,7 +338,7 @@
}
void
-IIC::insertBlock(Addr addr, BlkType* blk)
+IIC::insertBlock(Addr addr, BlkType* blk, int context_src)
{
}
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/iic.hh
--- a/src/mem/cache/tags/iic.hh Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/iic.hh Tue Jan 12 10:53:02 2010 -0800
@@ -422,7 +422,7 @@
* @param lat The access latency.
* @return A pointer to the block found, if any.
*/
- IICTag* accessBlock(Addr addr, int &lat);
+ IICTag* accessBlock(Addr addr, int &lat, int context_src);
/**
* Find the block, do not update the replacement data.
@@ -440,7 +440,7 @@
*/
IICTag* findVictim(Addr addr, PacketList &writebacks);
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Called at end of simulation to complete average block reference stats.
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/lru.cc
--- a/src/mem/cache/tags/lru.cc Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/lru.cc Tue Jan 12 10:53:02 2010 -0800
@@ -150,7 +150,7 @@
}
LRUBlk*
-LRU::accessBlock(Addr addr, int &lat)
+LRU::accessBlock(Addr addr, int &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
@@ -200,7 +200,7 @@
}
void
-LRU::insertBlock(Addr addr, LRU::BlkType *blk)
+LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src)
{
if (!blk->isTouched) {
tagsInUse++;
diff -r 6f8efbef2300 -r 5aec45d0fc24 src/mem/cache/tags/lru.hh
--- a/src/mem/cache/tags/lru.hh Tue Jan 12 10:22:46 2010 -0800
+++ b/src/mem/cache/tags/lru.hh Tue Jan 12 10:53:02 2010 -0800
@@ -172,7 +172,7 @@
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- LRUBlk* accessBlock(Addr addr, int &lat);
+ LRUBlk* accessBlock(Addr addr, int &lat, int context_src);
/**
* Finds the given address in the cache, do not update replacement data.
@@ -197,7 +197,7 @@
* @param addr The address to update.
* @param blk The block to update.
*/
- void insertBlock(Addr addr, BlkType *blk);
+ void insertBlock(Addr addr, BlkType *blk, int context_src);
/**
* Generate the tag from the given address.
--- End Message ---
