# HG changeset patch
# User Derek Hower <d...@cs.wisc.edu>
# Date 1252704179 18000
# Node ID 1a01f799bd7636f41cb864f99dd8d9184034cf72
# Parent ec28f4e6df9e636e78abbeec745afaee806375a3
ruby: cleaned up unified MESI/MOESI configuration
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -26,6 +26,7 @@
memory_size_mb = 1024
num_dma = 1
+#default protocol
protocol = "MESI_CMP_directory"
# check for overrides
@@ -56,7 +57,7 @@
net_ports = Array.new
iface_ports = Array.new
-#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with
protocol "+protocol);
+assert((protocol == "MESI_CMP_directory" or protocol ==
"MOESI_CMP_directory"), __FILE__+" cannot be used with protocol "+protocol);
require protocol+".rb"
@@ -71,9 +72,7 @@
icache, dcache,
sequencer,
num_l2_banks)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports <<
MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
"L1Cache",
icache, dcache,
@@ -87,17 +86,14 @@
net_ports <<
MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
"L2Cache",
cache)
- net_ports.last.request_latency = l2_cache_latency + 2
- net_ports.last.response_latency = l2_cache_latency + 2
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports <<
MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
"L2Cache",
cache)
end
-
+ net_ports.last.request_latency = l2_cache_latency + 2
+ net_ports.last.response_latency = l2_cache_latency + 2
}
num_memories.times { |n|
directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s,
memory_size_mb/num_memories)
@@ -107,9 +103,7 @@
"Directory",
directory,
memory_control)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports <<
MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
"Directory",
directory,
@@ -124,9 +118,7 @@
net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
"DMA",
dma_sequencer)
- end
-
- if protocol == "MESI_CMP_directory"
+ elsif protocol == "MESI_CMP_directory"
net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
"DMA",
dma_sequencer)
diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb
--- a/src/mem/ruby/config/cfg.rb
+++ b/src/mem/ruby/config/cfg.rb
@@ -296,9 +296,6 @@
end
-
-
-
class CacheController < NetPort
@@total_cache_controllers = Hash.new
@@ -438,27 +435,27 @@
cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0
cacti_args << 50 << 10 << 10 << 0 << 1 << 1
-# cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " +
cacti_args.join(" ")
+ cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join("
")
-# IO.popen(cacti_cmd) { |pipe|
-# str1 = pipe.readline
-# str2 = pipe.readline
-# results = str2.split(", ")
-# if results.size != 61
-# print "CACTI ERROR: CACTI produced unexpected output.\n"
-# print "Are you using the version shipped with libruby?\n"
-# raise Exception
-# end
-# latency_ns = results[5].to_f
-# if (latency_ns == "1e+39")
-# print "CACTI ERROR: CACTI was unable to realistically model the
cache ",@obj_name,"\n"
-# print "Either change the cache parameters or manually set the
latency values\n"
-# raise Exception
-# end
-# clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
-# latency_cycles = (latency_ns / clk_period_ns).ceil
-# @latency = latency_cycles
-# }
+ IO.popen(cacti_cmd) { |pipe|
+ str1 = pipe.readline
+ str2 = pipe.readline
+ results = str2.split(", ")
+ if results.size != 61
+ print "CACTI ERROR: CACTI produced unexpected output.\n"
+ print "Are you using the version shipped with libruby?\n"
+ raise Exception
+ end
+ latency_ns = results[5].to_f
+ if (latency_ns == "1e+39")
+ print "CACTI ERROR: CACTI was unable to realistically model the
cache ",@obj_name,"\n"
+ print "Either change the cache parameters or manually set the
latency values\n"
+ raise Exception
+ end
+ clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
+ latency_cycles = (latency_ns / clk_period_ns).ceil
+ @latency = latency_cycles
+ }
elsif @latency.is_a?(Float)
clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
latency_cycles = (@latency / clk_period_ns).ceil
@@ -757,5 +754,4 @@
end
end
-#added by SS
require "defaults.rb"
diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb
--- a/src/mem/ruby/config/defaults.rb
+++ b/src/mem/ruby/config/defaults.rb
@@ -9,7 +9,7 @@
# buffer_size limits the size of all other buffers connecting to
# SLICC Controllers. When 0, infinite buffering is used.
- default_param :buffer_size, Integer, 0
+ default_param :buffer_size, Integer, 32
# added by SS for TBE
default_param :number_of_TBEs, Integer, 256
@@ -36,19 +36,19 @@
# 1. change protocol_trace = true
# 2. enable debug in the Ruby Makefile
# 3. set start_time = 1
- default_param :protocol_trace, Boolean, true
+ default_param :protocol_trace, Boolean, false
# a string for filtering debugging output (for all g_debug vars see Debug.h)
- default_param :filter_string, String, "none"
+ default_param :filter_string, String, ""
# filters debugging messages based on priority (low, med, high)
- default_param :verbosity_string, String, "none"
+ default_param :verbosity_string, String, ""
# filters debugging messages based on a ruby time
default_param :start_time, Integer, 1
# sends debugging messages to a output filename
- default_param :output_filename, String, "debug_ss"
+ default_param :output_filename, String, ""
end
class Topology < LibRubyObject
@@ -167,6 +167,32 @@
default_param :response_latency, Integer, 14
end
+class MESI_CMP_directory_L2CacheController < CacheController
+ default_param :l2_request_latency, Integer, 2
+ default_param :l2_response_latency, Integer, 2
+ default_param :to_L1_latency, Integer, 1
+
+#if 0 then automatically calculated
+ default_param :lowest_bit, Integer, 0
+ default_param :highest_bit, Integer, 0
+end
+
+class MESI_CMP_directory_L1CacheController < L1CacheController
+ default_param :l1_request_latency, Integer, 2
+ default_param :l1_response_latency, Integer, 2
+ default_param :to_L2_latency, Integer, 1
+end
+
+
+class MESI_CMP_directory_DirectoryController < DirectoryController
+ default_param :to_mem_ctrl_latency, Integer, 1
+ default_param :directory_latency, Integer, 6
+end
+
+class MESI_CMP_directory_DMAController < DMAController
+ default_param :request_latency, Integer, 6
+end
+
class RubySystem
# Random seed used by the simulation. If set to "rand", the seed
@@ -206,29 +232,5 @@
end
#added by SS
-class MESI_CMP_directory_L2CacheController < CacheController
- default_param :l2_request_latency, Integer, 2
- default_param :l2_response_latency, Integer, 2
- default_param :to_L1_latency, Integer, 1
-#if 0 then automatically calculated
- default_param :lowest_bit, Integer, 0
- default_param :highest_bit, Integer, 0
-end
-class MESI_CMP_directory_L1CacheController < L1CacheController
- default_param :l1_request_latency, Integer, 2
- default_param :l1_response_latency, Integer, 2
- default_param :to_L2_latency, Integer, 1
-end
-
-
-class MESI_CMP_directory_DirectoryController < DirectoryController
- default_param :to_mem_ctrl_latency, Integer, 1
- default_param :directory_latency, Integer, 6
-end
-
-class MESI_CMP_directory_DMAController < DMAController
- default_param :request_latency, Integer, 6
-end
-
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -35,7 +35,7 @@
cpus = [ MemTest() for i in xrange(nb_cores) ]
import ruby_config
-ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
+ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
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