changeset ba1ff0a71710 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ba1ff0a71710
description:
inorder: update twolf regression
diffstat:
3 files changed, 143 insertions(+), 125 deletions(-)
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 3
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 6
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 259 +++++-----
diffs (truncated from 446 to 300 lines):
diff -r 0039707f915e -r ba1ff0a71710
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Mon Mar
22 23:39:23 2010 -0400
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Tue Mar
23 00:14:52 2010 -0400
@@ -79,6 +79,7 @@
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -113,6 +114,7 @@
latency=1000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10000
@@ -147,6 +149,7 @@
latency=10000
max_miss_count=0
mshrs=10
+num_cpus=1
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=100000
diff -r 0039707f915e -r ba1ff0a71710
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Mon Mar 22
23:39:23 2010 -0400
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Tue Mar 23
00:14:52 2010 -0400
@@ -5,9 +5,9 @@
All Rights Reserved
-M5 compiled Jan 29 2010 09:29:58
-M5 revision a196f8cf520a 6706 default qtip tip inorder_twolf_alpha
-M5 started Jan 29 2010 09:31:14
+M5 compiled Mar 22 2010 23:40:09
+M5 revision ec3385b5d6df 7040 default qtip tip inorder_twolf_update
+M5 started Mar 22 2010 23:40:10
M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink
build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
diff -r 0039707f915e -r ba1ff0a71710
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Mon Mar
22 23:39:23 2010 -0400
+++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Tue Mar
23 00:14:52 2010 -0400
@@ -1,53 +1,60 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 55182 #
Simulator instruction rate (inst/s)
-host_mem_usage 156168 #
Number of bytes of host memory used
-host_seconds 1665.47 #
Real time elapsed on the host
-host_tick_rate 59164617 #
Simulator tick rate (ticks/s)
+host_inst_rate 53958 #
Simulator instruction rate (inst/s)
+host_mem_usage 156280 #
Number of bytes of host memory used
+host_seconds 1703.24 #
Real time elapsed on the host
+host_tick_rate 57999569 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 91903056 #
Number of instructions simulated
-sim_seconds 0.098537 #
Number of seconds simulated
-sim_ticks 98536744000 #
Number of ticks simulated
+sim_seconds 0.098787 #
Number of seconds simulated
+sim_ticks 98787075000 #
Number of ticks simulated
system.cpu.AGEN-Unit.instReqsProcessed 26537108 #
Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.instReqsProcessed 92657148
# Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.predictedNotTaken 8232810
# Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 2041716
# Number of Branches Predicted As Taken (True).
-system.cpu.Decode-Unit.instReqsProcessed 92657148 #
Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.BTBHits 5943749 #
Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups 9141724 #
Number of BTB lookups
+system.cpu.Branch-Predictor.RASInCorrect 1029596 #
Number of incorrect RAS predictions.
+system.cpu.Branch-Predictor.condIncorrect 11377435 #
Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condPredicted 7465155 #
Number of conditional branches predicted
+system.cpu.Branch-Predictor.instReqsProcessed 92001832
# Number of Instructions Requests that completed in this resource.
+system.cpu.Branch-Predictor.lookups 10240963 #
Number of BP lookups
+system.cpu.Branch-Predictor.predictedNotTaken 2255511
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 7985452
# Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.usedRAS 1029596 #
Number of times the RAS was used to get a target.
+system.cpu.Decode-Unit.instReqsProcessed 92001832 #
Number of Instructions Requests that completed in this resource.
system.cpu.Execution-Unit.cyclesExecuted 64907308 #
Number of Cycles Execution Unit was used.
system.cpu.Execution-Unit.instReqsProcessed 64907696
# Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 3739118
# Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect 1029596
# Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Execution-Unit.utilization 0.329356 #
Utilization of Execution Unit (cycles / totalCycles).
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 191370621
# Number of Instructions Requests that completed in this resource.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 78179
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 3313804
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Execution-Unit.utilization 0.328521 #
Utilization of Execution Unit (cycles / totalCycles).
+system.cpu.Fetch-Seq-Unit.instReqsProcessed 195282323
# Number of Instructions Requests that completed in this resource.
system.cpu.Graduation-Unit.instReqsProcessed 91903056
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.divInstReqsProcessed 0
# Number of Divide Requests Processed.
system.cpu.Mult-Div-Unit.instReqsProcessed 916504
# Number of Instructions Requests that completed in this resource.
system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252
# Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 196152134
# Number of Instructions Requests that completed in this resource.
-system.cpu.activity 96.743392 #
Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.instReqsProcessed 196152147
# Number of Instructions Requests that completed in this resource.
+system.cpu.activity 96.136450 #
Percentage of cycles cpu is active
system.cpu.committedInsts 91903056 #
Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 #
Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 #
Number of context switches
-system.cpu.cpi 2.144363 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.144363 #
CPI: Total CPI of All Threads
+system.cpu.cpi 2.149810 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.149810 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51569.473684
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48547.368421
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51560
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48531.578947
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995723 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 24495500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 24491000 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 475 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 23060000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 23052500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56295.857988
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53295.857988
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56135.825713
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53135.825713
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 6499244 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 104654000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 104356500 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000286 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1859 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 99077000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 98779500
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1859 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
@@ -59,29 +66,31 @@
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55333.976007 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52329.477292
# average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 55204.584404 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52198.800343
# average overall mshr miss latency
system.cpu.dcache.demand_hits 26494967 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 129149500 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 128847500 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000088 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 2334 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 122137000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 121832000
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000088 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2334 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0 0.352013 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1441.845036 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55333.976007
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52329.477292
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55204.584404
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52198.800343
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 26494967 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 129149500 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 128847500 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000088 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 2334 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 122137000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 121832000
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000088 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2334 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -89,7 +98,7 @@
system.cpu.dcache.replacements 157 #
number of replacements
system.cpu.dcache.sampled_refs 2223 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.684134 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.845036 #
Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 #
Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 #
number of writebacks
@@ -110,71 +119,73 @@
system.cpu.dtb.write_acv 0 #
DTB write access violations
system.cpu.dtb.write_hits 6501103 #
DTB write hits
system.cpu.dtb.write_misses 23 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 98713473 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27258.057090
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23994.339402
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 98704785 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 236818000 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000088 #
miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 8688 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 120 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 205583500
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 8568 #
number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 103280491 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 27107.378354
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 23969.601677
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 103271695 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 238436500 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000085 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 8796 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 210 #
number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 205803000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000083 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 8586 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 1000
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 11520.166317 #
Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles::no_targets 2500
# average number of cycles each access was blocked
+system.cpu.icache.avg_refs 12027.916958 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 1000
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 2500
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 98713473 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27258.057090 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23994.339402
# average overall mshr miss latency
-system.cpu.icache.demand_hits 98704785 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 236818000 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000088 #
miss rate for demand accesses
-system.cpu.icache.demand_misses 8688 #
number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 120 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 205583500
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000087 #
mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 8568 #
number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 103280491 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 27107.378354 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 23969.601677
# average overall mshr miss latency
+system.cpu.icache.demand_hits 103271695 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 238436500 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000085 #
miss rate for demand accesses
+system.cpu.icache.demand_misses 8796 #
number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 210 #
number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 205803000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000083 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 8586 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 98713473 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27258.057090
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23994.339402
# average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.697585 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1428.655102 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 103280491 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 27107.378354
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 23969.601677
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 98704785 #
number of overall hits
-system.cpu.icache.overall_miss_latency 236818000 #
number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000088 #
miss rate for overall accesses
-system.cpu.icache.overall_misses 8688 #
number of overall misses
-system.cpu.icache.overall_mshr_hits 120 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 205583500
# number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000087 #
mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 8568 #
number of overall MSHR misses
+system.cpu.icache.overall_hits 103271695 #
number of overall hits
+system.cpu.icache.overall_miss_latency 238436500 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000085 #
miss rate for overall accesses
+system.cpu.icache.overall_misses 8796 #
number of overall misses
+system.cpu.icache.overall_mshr_hits 210 #
number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 205803000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000083 #
mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 8586 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 6734 #
number of replacements
-system.cpu.icache.sampled_refs 8568 #
Sample count of references to valid blocks.
+system.cpu.icache.replacements 6752 #
number of replacements
+system.cpu.icache.sampled_refs 8586 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1428.229557 #
Cycle average of tags in use
-system.cpu.icache.total_refs 98704785 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1428.655102 #
Cycle average of tags in use
+system.cpu.icache.total_refs 103271695 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.icache_port.instReqsProcessed 98713472 #
Number of Instructions Requests that completed in this resource.
-system.cpu.idleCycles 6417911 #
Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.466339 #
IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.466339 #
IPC: Total IPC of All Threads
+system.cpu.icache_port.instReqsProcessed 103280490 #
Number of Instructions Requests that completed in this resource.
+system.cpu.idleCycles 7633377 #
Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.465157 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.465157 #
IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_hits 0 #
DTB hits
system.cpu.itb.data_misses 0 #
DTB misses
-system.cpu.itb.fetch_accesses 98713520 #
ITB accesses
+system.cpu.itb.fetch_accesses 103280539 #
ITB accesses
system.cpu.itb.fetch_acv 0 #
ITB acv
-system.cpu.itb.fetch_hits 98713473 #
ITB hits
+system.cpu.itb.fetch_hits 103280492 #
ITB hits
system.cpu.itb.fetch_misses 47 #
ITB misses
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