Hi Gabe, Basically, no, I don't take into account any of these situations. They do need to be dealt with, but at the moment the version in there doesn't do that. It would probably be simple to add in though.
Cheers Tim On Thu, 25 Mar 2010 14:14:09 -0400, Gabriel Michael Black <gbl...@eecs.umich.edu> wrote: > Hi Tim. I noticed in your comments that you say you copy the flags > from the individual tranlstions into the main request object. I don't > remember my version doing that, but it might have. Have you accounted > for situations where the different translations would have different > properties? For instance, what if someone reads at a page boundary > where one page is cacheable and the other isn't? > > Gabe > > Quoting "Timothy M. Jones" <tjon...@inf.ed.ac.uk>: > >> changeset a06e95c99294 in /z/repo/m5 >> details: http://repo.m5sim.org/m5?cmd=changeset;node=a06e95c99294 >> description: >> CPU: Added comments to address translation classes. >> >> diffstat: >> >> 1 file changed, 62 insertions(+), 2 deletions(-) >> src/cpu/translation.hh | 64 >> ++++++++++++++++++++++++++++++++++++++++++++++-- >> >> diffs (153 lines): >> >> diff -r 2ab58c54de63 -r a06e95c99294 src/cpu/translation.hh >> --- a/src/cpu/translation.hh Tue Mar 23 22:49:43 2010 -0700 >> +++ b/src/cpu/translation.hh Thu Mar 25 12:43:52 2010 +0000 >> @@ -35,6 +35,16 @@ >> >> #include "sim/tlb.hh" >> >> +/** >> + * This class captures the state of an address translation. A >> translation >> + * can be split in two if the ISA supports it and the memory access >> crosses >> + * a page boundary. In this case, this class is shared by two data >> + * translations (below). Otherwise it is used by a single data >> translation >> + * class. When each part of the translation is finished, the finish >> + * function is called which will indicate whether the whole >> translation is >> + * completed or not. There are also functions for accessing parts of >> the >> + * translation state which deal with the possible split correctly. >> + */ >> class WholeTranslationState >> { >> protected: >> @@ -50,7 +60,10 @@ >> uint64_t *res; >> BaseTLB::Mode mode; >> >> - /** Single translation state. */ >> + /** >> + * Single translation state. We set the number of outstanding >> + * translations to one and indicate that it is not split. >> + */ >> WholeTranslationState(RequestPtr _req, uint8_t *_data, uint64_t >> *_res, >> BaseTLB::Mode _mode) >> : outstanding(1), isSplit(false), mainReq(_req), sreqLow(NULL), >> @@ -60,7 +73,11 @@ >> assert(mode == BaseTLB::Read || mode == BaseTLB::Write); >> } >> >> - /** Split translation state. */ >> + /** >> + * Split translation state. We copy all state into this class, >> set the >> + * number of outstanding translations to two and then mark this as >> a >> + * split translation. >> + */ >> WholeTranslationState(RequestPtr _req, RequestPtr _sreqLow, >> RequestPtr _sreqHigh, uint8_t *_data, >> uint64_t *_res, >> BaseTLB::Mode _mode) >> @@ -71,6 +88,13 @@ >> assert(mode == BaseTLB::Read || mode == BaseTLB::Write); >> } >> >> + /** >> + * Finish part of a translation. If there is only one request >> then this >> + * translation is completed. If the request has been split in two >> then >> + * the outstanding count determines whether the translation is >> complete. >> + * In this case, flags from the split request are copied to the >> main >> + * request to make it easier to access them later on. >> + */ >> bool >> finish(Fault fault, int index) >> { >> @@ -89,6 +113,10 @@ >> return outstanding == 0; >> } >> >> + /** >> + * Determine whether this translation produced a fault. Both >> parts of the >> + * translation must be checked if this is a split translation. >> + */ >> Fault >> getFault() const >> { >> @@ -102,36 +130,54 @@ >> return NoFault; >> } >> >> + /** Remove all faults from the translation. */ >> void >> setNoFault() >> { >> faults[0] = faults[1] = NoFault; >> } >> >> + /** >> + * Check if this request is uncacheable. We only need to check >> the main >> + * request because the flags will have been copied here on a split >> + * translation. >> + */ >> bool >> isUncacheable() const >> { >> return mainReq->isUncacheable(); >> } >> >> + /** >> + * Check if this request is a prefetch. We only need to check the >> main >> + * request because the flags will have been copied here on a split >> + * translation. >> + */ >> bool >> isPrefetch() const >> { >> return mainReq->isPrefetch(); >> } >> >> + /** Get the physical address of this request. */ >> Addr >> getPaddr() const >> { >> return mainReq->getPaddr(); >> } >> >> + /** >> + * Get the flags associated with this request. We only need to >> access >> + * the main request because the flags will have been copied here >> on a >> + * split translation. >> + */ >> unsigned >> getFlags() >> { >> return mainReq->getFlags(); >> } >> >> + /** Delete all requests that make up this translation. */ >> void >> deleteReqs() >> { >> @@ -143,6 +189,16 @@ >> } >> }; >> >> + >> +/** >> + * This class represents part of a data address translation. All >> state for >> + * the translation is held in WholeTranslationState (above). >> Therefore this >> + * class does not need to know whether the translation is split or >> not. The >> + * index variable determines this but is simply passed on to the >> state class. >> + * When this part of the translation is completed, finish is called. >> If the >> + * translation state class indicate that the whole translation is >> complete >> + * then the execution context is informed. >> + */ >> template <class ExecContext> >> class DataTranslation : public BaseTLB::Translation >> { >> @@ -163,6 +219,10 @@ >> { >> } >> >> + /** >> + * Finish this part of the translation and indicate that the whole >> + * translation is complete if the state says so. >> + */ >> void >> finish(Fault fault, RequestPtr req, ThreadContext *tc, >> BaseTLB::Mode mode) >> _______________________________________________ >> m5-dev mailing list >> m5-dev@m5sim.org >> http://m5sim.org/mailman/listinfo/m5-dev >> > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > -- Timothy M. Jones http://homepages.inf.ed.ac.uk/tjones1 The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
