changeset ddd77866bf82 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ddd77866bf82
description:
inorder: update regressions
diffstat:
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout | 8 +-
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 333 +++++----
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout | 8 +-
tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 274 ++++----
tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout | 10 +-
tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 212 +++---
tests/quick/00.hello/ref/mips/linux/inorder-timing/simout | 10 +-
tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt | 176 ++--
8 files changed, 519 insertions(+), 512 deletions(-)
diffs (truncated from 1613 to 300 lines):
diff -r 0466c41f63cd -r ddd77866bf82
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Wed Jun
23 18:21:12 2010 -0400
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Wed Jun
23 18:21:44 2010 -0400
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled May 12 2010 01:43:39
-M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip
-M5 started May 12 2010 01:54:51
-M5 executing on zizzer
+M5 compiled Jun 23 2010 16:05:32
+M5 revision f157e4974de9+ 7462+ default qtip inorder_update_regr tip
+M5 started Jun 23 2010 16:57:34
+M5 executing on zooks
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re
tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff -r 0466c41f63cd -r ddd77866bf82
tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
--- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Wed Jun
23 18:21:12 2010 -0400
+++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Wed Jun
23 18:21:44 2010 -0400
@@ -1,60 +1,64 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 55482 #
Simulator instruction rate (inst/s)
-host_mem_usage 223108 #
Number of bytes of host memory used
-host_seconds 1592.24 #
Real time elapsed on the host
-host_tick_rate 66617861 #
Simulator tick rate (ticks/s)
+host_inst_rate 51467 #
Simulator instruction rate (inst/s)
+host_mem_usage 168500 #
Number of bytes of host memory used
+host_seconds 1716.45 #
Real time elapsed on the host
+host_tick_rate 61684615 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 88340673 #
Number of instructions simulated
-sim_seconds 0.106071 #
Number of seconds simulated
-sim_ticks 106071426500 #
Number of ticks simulated
-system.cpu.AGEN-Unit.instReqsProcessed 35224018 #
Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.BTBHits 4715785 #
Number of BTB hits
-system.cpu.Branch-Predictor.BTBLookups 11658962 #
Number of BTB lookups
-system.cpu.Branch-Predictor.RASInCorrect 1659877 #
Number of incorrect RAS predictions.
-system.cpu.Branch-Predictor.condIncorrect 10683155 #
Number of conditional branches incorrect
-system.cpu.Branch-Predictor.condPredicted 8920904 #
Number of conditional branches predicted
-system.cpu.Branch-Predictor.instReqsProcessed 88352585
# Number of Instructions Requests that completed in this resource.
-system.cpu.Branch-Predictor.lookups 13755709 #
Number of BP lookups
-system.cpu.Branch-Predictor.predictedNotTaken 5728293
# Number of Branches Predicted As Not Taken (False).
-system.cpu.Branch-Predictor.predictedTaken 8027416
# Number of Branches Predicted As Taken (True).
-system.cpu.Branch-Predictor.usedRAS 1659877 #
Number of times the RAS was used to get a target.
-system.cpu.Decode-Unit.instReqsProcessed 88352585 #
Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.cyclesExecuted 53070972 #
Number of Cycles Execution Unit was used.
-system.cpu.Execution-Unit.instReqsProcessed 53075554
# Number of Instructions Requests that completed in this resource.
-system.cpu.Execution-Unit.predictedNotTakenIncorrect 393312
# Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.Execution-Unit.predictedTakenIncorrect 2262427
# Number of Branches Incorrectly Predicted As Taken.
-system.cpu.Execution-Unit.utilization 0.250166 #
Utilization of Execution Unit (cycles / totalCycles).
-system.cpu.Fetch-Seq-Unit.instReqsProcessed 187375293
# Number of Instructions Requests that completed in this resource.
-system.cpu.Graduation-Unit.instReqsProcessed 88340673
# Number of Instructions Requests that completed in this resource.
-system.cpu.Mult-Div-Unit.divInstReqsProcessed 0
# Number of Divide Requests Processed.
-system.cpu.Mult-Div-Unit.instReqsProcessed 82202
# Number of Instructions Requests that completed in this resource.
-system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101
# Number of Multiply Requests Processed.
-system.cpu.RegFile-Manager.instReqsProcessed 165543836
# Number of Instructions Requests that completed in this resource.
-system.cpu.activity 85.696841 #
Percentage of cycles cpu is active
+sim_seconds 0.105878 #
Number of seconds simulated
+sim_ticks 105878306500 #
Number of ticks simulated
+system.cpu.AGEN-Unit.agens 35224018 #
Number of Address Generations
+system.cpu.Branch-Predictor.BTBHitPct 40.484338 #
BTB Hit Percentage
+system.cpu.Branch-Predictor.BTBHits 4662108 #
Number of BTB hits
+system.cpu.Branch-Predictor.BTBLookups 11515831 #
Number of BTB lookups
+system.cpu.Branch-Predictor.RASInCorrect 1659774 #
Number of incorrect RAS predictions.
+system.cpu.Branch-Predictor.condIncorrect 2359487 #
Number of conditional branches incorrect
+system.cpu.Branch-Predictor.condPredicted 8920848 #
Number of conditional branches predicted
+system.cpu.Branch-Predictor.lookups 13754477 #
Number of BP lookups
+system.cpu.Branch-Predictor.predictedNotTaken 5781163
# Number of Branches Predicted As Not Taken (False).
+system.cpu.Branch-Predictor.predictedTaken 7973314
# Number of Branches Predicted As Taken (True).
+system.cpu.Branch-Predictor.usedRAS 1659774 #
Number of times the RAS was used to get a target.
+system.cpu.Execution-Unit.executions 53075554 #
Number of Instructions Executed.
+system.cpu.Execution-Unit.predictedNotTakenIncorrect 485820
# Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.Execution-Unit.predictedTakenIncorrect 1873667
# Number of Branches Incorrectly Predicted As Taken.
+system.cpu.Mult-Div-Unit.divides 0 #
Number of Divide Operations Executed
+system.cpu.Mult-Div-Unit.multiplies 41101 #
Number of Multipy Operations Executed
+system.cpu.RegFile-Manager.regFileAccesses 156428919
# Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 103882038 #
Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileWrites 52546881 #
Number of Writes to Register File
+system.cpu.RegFile-Manager.regForwards 2136327 #
Number of Registers Read Through Forwarding Logic
+system.cpu.activity 85.568977 #
Percentage of cycles cpu is active
+system.cpu.comBranches 13754477 #
Number of Branches instructions committed
+system.cpu.comFloats 151453 #
Number of Floating Point instructions committed
+system.cpu.comInts 30457224 #
Number of Integer instructions committed
+system.cpu.comLoads 20379399 #
Number of Load instructions committed
+system.cpu.comNonSpec 4583 #
Number of Non-Speculative instructions committed
+system.cpu.comNops 8748916 #
Number of Nop instructions committed
+system.cpu.comStores 14844619 #
Number of Store instructions committed
system.cpu.committedInsts 88340673 #
Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 #
Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 #
Number of context switches
-system.cpu.cpi 2.401417 #
CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.401418 #
CPI: Total CPI of All Threads
+system.cpu.cpi 2.397046 #
CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.397046 #
CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38148.092683
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35044.037784
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38170.794523
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35065.488925
# average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2318107000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2319486500 #
number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 #
miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2129486000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2130789500
# number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 #
mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56431.835934
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53431.835934
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 56329.688303
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53329.688303
# average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 14463584 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8453094000 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 8437793000 #
number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.010250 #
miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 149793 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8003715000
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 7988414000
# number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 #
mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 149793 #
number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
@@ -66,31 +70,31 @@
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51155.262895 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48125.233308
# average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 51089.146035 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48058.755503
# average overall mshr miss latency
system.cpu.dcache.demand_hits 34679456 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10771201000 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 10757279500 #
number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.006035 #
miss rate for demand accesses
system.cpu.dcache.demand_misses 210559 #
number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10133201000
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 10119203500
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.006035 #
mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 210559 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995316 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4076.814935 #
Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.995318 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4076.822350 #
Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51155.262895
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48125.233308
# average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 51089.146035
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48058.755503
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 34679456 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 10771201000 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 10757279500 #
number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.006035 #
miss rate for overall accesses
system.cpu.dcache.overall_misses 210559 #
number of overall misses
system.cpu.dcache.overall_mshr_hits 0 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10133201000
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 10119203500
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.006035 #
mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 210559 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
@@ -98,11 +102,10 @@
system.cpu.dcache.replacements 200248 #
number of replacements
system.cpu.dcache.sampled_refs 204344 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.814935 #
Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.822350 #
Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 843108000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 841843000 #
Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 147714 #
number of writebacks
-system.cpu.dcache_port.instReqsProcessed 35224018 #
Number of Instructions Requests that completed in this resource.
system.cpu.dtb.data_accesses 34987415 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
system.cpu.dtb.data_hits 34890015 #
DTB hits
@@ -119,74 +122,73 @@
system.cpu.dtb.write_acv 0 #
DTB write access violations
system.cpu.dtb.write_hits 14613377 #
DTB write hits
system.cpu.dtb.write_misses 7252 #
DTB write misses
-system.cpu.icache.ReadReq_accesses 99022487 #
number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18976.095303
# average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15795.359051
# average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 98940181 #
number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1561846500 #
number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000831 #
miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 82306 #
number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 3529 #
number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1244311000
# number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000796 #
mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 78777 #
number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 98672431 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 19067.834064
# average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15854.703492
# average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 98591653 #
number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1540261500 #
number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000819 #
miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 80778 #
number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3006 #
number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 1233052000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000788 #
mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 77772 #
number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 10666.666667
# average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1255.952638 #
Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles::no_targets 800
# average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1267.701139 #
Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 3 #
number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 5 #
number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 32000
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 4000
# number of cycles access was blocked
system.cpu.icache.cache_copies 0 #
number of cache copies performed
-system.cpu.icache.demand_accesses 99022487 #
number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 18976.095303 #
average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15795.359051
# average overall mshr miss latency
-system.cpu.icache.demand_hits 98940181 #
number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1561846500 #
number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000831 #
miss rate for demand accesses
-system.cpu.icache.demand_misses 82306 #
number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 3529 #
number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1244311000
# number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000796 #
mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 78777 #
number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 98672431 #
number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 19067.834064 #
average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15854.703492
# average overall mshr miss latency
+system.cpu.icache.demand_hits 98591653 #
number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1540261500 #
number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000819 #
miss rate for demand accesses
+system.cpu.icache.demand_misses 80778 #
number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3006 #
number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 1233052000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000788 #
mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 77772 #
number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 #
number of fast writes performed
system.cpu.icache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.914772 #
Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1873.453452 #
Average occupied blocks per context
-system.cpu.icache.overall_accesses 99022487 #
number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 18976.095303
# average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15795.359051
# average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.914796 #
Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1873.502207 #
Average occupied blocks per context
+system.cpu.icache.overall_accesses 98672431 #
number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 19067.834064
# average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15854.703492
# average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 98940181 #
number of overall hits
-system.cpu.icache.overall_miss_latency 1561846500 #
number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000831 #
miss rate for overall accesses
-system.cpu.icache.overall_misses 82306 #
number of overall misses
-system.cpu.icache.overall_mshr_hits 3529 #
number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1244311000
# number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000796 #
mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 78777 #
number of overall MSHR misses
+system.cpu.icache.overall_hits 98591653 #
number of overall hits
+system.cpu.icache.overall_miss_latency 1540261500 #
number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000819 #
miss rate for overall accesses
+system.cpu.icache.overall_misses 80778 #
number of overall misses
+system.cpu.icache.overall_mshr_hits 3006 #
number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 1233052000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000788 #
mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 77772 #
number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 76731 #
number of replacements
-system.cpu.icache.sampled_refs 78777 #
Sample count of references to valid blocks.
+system.cpu.icache.replacements 75726 #
number of replacements
+system.cpu.icache.sampled_refs 77772 #
Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1873.453452 #
Cycle average of tags in use
-system.cpu.icache.total_refs 98940181 #
Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1873.502207 #
Cycle average of tags in use
+system.cpu.icache.total_refs 98591653 #
Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 #
number of writebacks
-system.cpu.icache_port.instReqsProcessed 99022707 #
Number of Instructions Requests that completed in this resource.
-system.cpu.idleCycles 30343130 #
Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.416421 #
IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.416421 #
IPC: Total IPC of All Threads
+system.cpu.idleCycles 30558645 #
Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.417180 #
IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.417180 #
IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 #
DTB accesses
system.cpu.itb.data_acv 0 #
DTB access violations
system.cpu.itb.data_hits 0 #
DTB hits
system.cpu.itb.data_misses 0 #
DTB misses
-system.cpu.itb.fetch_accesses 99026503 #
ITB accesses
+system.cpu.itb.fetch_accesses 98676443 #
ITB accesses
system.cpu.itb.fetch_acv 0 #
ITB acv
-system.cpu.itb.fetch_hits 99022489 #
ITB hits
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