I got the SPARC InOrderCPU to compile. But now this is happening: M5 compiled Jun 30 2010 12:26:11 M5 revision edde97a6ea7c+ 7069+ default tip M5 started Jun 30 2010 12:27:30 M5 executing on bellatrix command line: ./build/SPARC_SE/m5.fast configs/example/se.py -n 2 --inorder --caches --l2cache -c meu/hello Global frequency set at 1000000000000 ticks per second 0: system.remote_gdb.listener: listening for remote gdb on port 7000 0: system.remote_gdb.listener: listening for remote gdb on port 7001 **** REAL SIMULATION **** info: Entering event queue @ 0. Starting simulation... panic: eaComp not defined! @ cycle 59500 [eaComp:build/SPARC_SE/cpu/static_inst_exec_sigs.hh, line 18] Memory Usage: 581288 KBytes For more information see: http://www.m5sim.org/panic/b960c21d Program aborted at cycle 59500 Aborted
I've read that eaComp was removed from Mips and Alpha and should be removed from the others too. What has to be changed? Thanks, -- Eberle A. Rambo. On Wed, Jun 23, 2010 at 3:40 PM, Korey Sewell <ksew...@umich.edu> wrote: > oh, > if you do get into developing SPARC support for the inorder model, let's > move the discussion to the m5-dev@m5sim.org list which would be the more > appropriate discussion board. > > > On Wed, Jun 23, 2010 at 11:58 AM, Eberle <rambo.u...@gmail.com> wrote: > >> I tried and I get a compilation error: >> >> g++ -o build/SPARC_SE/cpu/inorder/inorder_cpu_builder.fo -c >> -Wno-deprecated -pipe -fno-strict-aliasing -Wall -Wno-sign-compare -Wundef >> -O3 -Werror -DNDEBUG -DTRACING_ON=0 -Ibuild/gzstream -Ibuild/libelf -Iext >> -I/usr/include/python2.6 -Ibuild/SPARC_SE >> build/SPARC_SE/cpu/inorder/inorder_cpu_builder.cc >> In file included from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.hh:42, >> from build/SPARC_SE/cpu/inorder/cpu.hh:52, >> from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc:42: >> build/SPARC_SE/arch/mt.hh:1:28: error: arch/sparc/mt.hh: No such file or >> directory >> In file included from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.hh:42, >> from build/SPARC_SE/cpu/inorder/pipeline_traits.cc:33: >> build/SPARC_SE/arch/mt.hh:1:28: error: arch/sparc/mt.hh: No such file or >> directory >> In file included from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.hh:42, >> from build/SPARC_SE/cpu/inorder/cpu.hh:52, >> from >> build/SPARC_SE/cpu/inorder/inorder_cpu_builder.cc:37: >> build/SPARC_SE/arch/mt.hh:1:28: error: arch/sparc/mt.hh: No such file or >> directory >> g++ -o build/SPARC_SE/cpu/inorder/inorder_trace.fo -c -Wno-deprecated >> -pipe -fno-strict-aliasing -Wall -Wno-sign-compare -Wundef -O3 -Werror >> -DNDEBUG -DTRACING_ON=0 -Ibuild/gzstream -Ibuild/libelf -Iext >> -I/usr/include/python2.6 -Ibuild/SPARC_SE >> build/SPARC_SE/cpu/inorder/inorder_trace.cc >> g++ -o build/SPARC_SE/cpu/inorder/pipeline_stage.fo -c -Wno-deprecated >> -pipe -fno-strict-aliasing -Wall -Wno-sign-compare -Wundef -O3 -Werror >> -DNDEBUG -DTRACING_ON=0 -Ibuild/gzstream -Ibuild/libelf -Iext >> -I/usr/include/python2.6 -Ibuild/SPARC_SE >> build/SPARC_SE/cpu/inorder/pipeline_stage.cc >> In file included from build/SPARC_SE/cpu/inorder/cpu.hh:56, >> from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc:42: >> build/SPARC_SE/cpu/inorder/reg_dep_map.hh:49: error: 'TotalNumRegs' is not >> a member of 'SparcISA' >> In file included from build/SPARC_SE/cpu/inorder/inorder_dyn_inst.hh:42, >> from build/SPARC_SE/cpu/inorder/pipeline_stage.hh:40, >> from build/SPARC_SE/cpu/inorder/pipeline_stage.cc:34: >> build/SPARC_SE/arch/mt.hh:1:28: error: arch/sparc/mt.hh: No such file or >> directory >> build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc: In member function >> 'virtual SparcISA::MiscReg InOrderDynInst::readRegOtherThread(unsigned int, >> ThreadID)': >> build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc:516: error: >> 'getTargetThread' is not a member of 'SparcISA' >> build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc: In member function >> 'virtual void InOrderDynInst::setRegOtherThread(unsigned int, const >> SparcISA::MiscReg&, ThreadID)': >> build/SPARC_SE/cpu/inorder/inorder_dyn_inst.cc:593: error: >> 'getTargetThread' is not a member of 'SparcISA' >> In file included from build/SPARC_SE/cpu/inorder/cpu.hh:56, >> from >> build/SPARC_SE/cpu/inorder/inorder_cpu_builder.cc:37: >> build/SPARC_SE/cpu/inorder/reg_dep_map.hh:49: error: 'TotalNumRegs' is not >> a member of 'SparcISA' >> In file included from build/SPARC_SE/cpu/inorder/resources/use_def.hh:44, >> from >> build/SPARC_SE/cpu/inorder/resources/resource_list.hh:37, >> from build/SPARC_SE/cpu/inorder/pipeline_traits.cc:34: >> build/SPARC_SE/cpu/inorder/reg_dep_map.hh:49: error: 'TotalNumRegs' is not >> a member of 'SparcISA' >> scons: *** [build/SPARC_SE/cpu/inorder/inorder_cpu_builder.fo] Error 1 >> scons: *** [build/SPARC_SE/cpu/inorder/inorder_dyn_inst.fo] Error 1 >> scons: *** [build/SPARC_SE/cpu/inorder/pipeline_traits.fo] Error 1 >> In file included from build/SPARC_SE/cpu/inorder/cpu.hh:56, >> from build/SPARC_SE/cpu/inorder/resource_pool.hh:45, >> from build/SPARC_SE/cpu/inorder/pipeline_stage.cc:35: >> build/SPARC_SE/cpu/inorder/reg_dep_map.hh:49: error: 'TotalNumRegs' is not >> a member of 'SparcISA' >> scons: *** [build/SPARC_SE/cpu/inorder/pipeline_stage.fo] Error 1 >> scons: building terminated because of errors. >> >> >> And, well, if I compile M5 without modifying scons, i get the following >> expected error: >> >> eberl...@bellatrix:~/UFSC/Workspaces/work_m5/m5$ ./build/SPARC_SE/m5.fast >> configs/example/se.py -n 2 --inorder --caches --l2cache -c meu/hello >> M5 Simulator System >> >> Copyright (c) 2001-2008 >> The Regents of The University of Michigan >> All Rights Reserved >> >> >> M5 compiled Jun 23 2010 12:50:36 >> M5 revision edde97a6ea7c+ 7069+ default tip >> M5 started Jun 23 2010 12:56:44 >> M5 executing on bellatrix >> command line: ./build/SPARC_SE/m5.fast configs/example/se.py -n 2 >> --inorder --caches --l2cache -c meu/hello >> Traceback (most recent call last): >> File "<string>", line 1, in <module> >> File "/home/eberle18/UFSC/Workspaces/work_m5/m5/src/python/m5/main.py", >> line 359, in main >> exec filecode in scope >> File "configs/example/se.py", line 137, in <module> >> (CPUClass, test_mem_mode, FutureClass) = >> Simulation.setCPUClass(options) >> File >> "/home/eberle18/UFSC/Workspaces/work_m5/m5/configs/common/Simulation.py", >> line 53, in setCPUClass >> class TmpClass(InOrderCPU): pass >> NameError: global name 'InOrderCPU' is not defined >> >> -- >> Eberle A. Rambo. >> >> >> >> On Wed, Jun 23, 2010 at 12:13 PM, soumyaroop roy <s...@cse.usf.edu>wrote: >> >>> Hello Eberle: >>> >>> Did you try inorder in the SPARC_SE mode yet? If yes, what errors did >>> you get? If no, could you try simulating a program, say the >>> /tests/quick/00.hello test, with the incorder cpu in SPARC_SE mode and >>> tell us what errors you see? >>> >>> regards, >>> Soumyaroop >>> >>> On Wed, Jun 23, 2010 at 9:50 AM, Eberle <rambo.u...@gmail.com> wrote: >>> > Hi Soumyaroop, >>> > >>> > Do you, or someone else, can say what needs to be done to make >>> InOrderCPU >>> > work with SPARC? >>> > What needs to be adapted, filenames... hints? >>> > >>> > >>> > >>> > Eberle >>> > >>> > >>> > On Tue, Jun 22, 2010 at 11:34 AM, soumyaroop roy <s...@cse.usf.edu> >>> wrote: >>> >> >>> >> Hello Eberle: >>> >> >>> >> On Tue, Jun 22, 2010 at 10:04 AM, Eberle <rambo.u...@gmail.com> >>> wrote: >>> >> > I've read the thread about SPARC_FS and InOrderCPU, but I need to >>> know >>> >> > whether it works with SPARC_SE. >>> >> >>> >> Currently, SPARC ISA is not supported in InOrderCPU >>> >> (http://m5sim.org/wiki/index.php/InOrder_ToDo_List). FS is currently >>> >> not supported for any ISA. >>> >> >>> >> > >>> >> > >>> >> > And also: The TimingSimpleCPU is equivalent to InOrderCPU, in terms >>> of >>> >> > pipeline and memory access (reordering)? >>> >> >>> >> TimingSimpleCPU does not model a CPU pipeline. >>> >> >>> >> Please refer to the documentation of these CPUs here: >>> >> >>> >> TimingSimpleCPU: >>> >> http://m5sim.org/wiki/index.php/SimpleCPU >>> >> >>> >> InOrderCpu: >>> >> http://m5sim.org/wiki/index.php/InOrder >>> >> >>> >> > >>> >> > >>> >> > >>> >> > -- >>> >> > Eberle A. Rambo. >>> >> >>> >> regards, >>> >> Soumyaroop >>> >> >>> >> > >>> >> > _______________________________________________ >>> >> > m5-users mailing list >>> >> > m5-us...@m5sim.org >>> >> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> > >>> >> >>> >> >>> >> >>> >> -- >>> >> Soumyaroop Roy >>> >> Ph.D. Candidate >>> >> Department of Computer Science and Engineering >>> >> University of South Florida, Tampa >>> >> http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy> >>> >> _______________________________________________ >>> >> m5-users mailing list >>> >> m5-us...@m5sim.org >>> >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> > >>> > >>> > _______________________________________________ >>> > m5-users mailing list >>> > m5-us...@m5sim.org >>> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> > >>> >>> >>> >>> -- >>> Soumyaroop Roy >>> Ph.D. Candidate >>> Department of Computer Science and Engineering >>> University of South Florida, Tampa >>> http://www.csee.usf.edu/~sroy <http://www.csee.usf.edu/%7Esroy> >>> _______________________________________________ >>> m5-users mailing list >>> m5-us...@m5sim.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >>> >> >> >> _______________________________________________ >> m5-users mailing list >> m5-us...@m5sim.org >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > > -- > - Korey > > _______________________________________________ > m5-users mailing list > m5-us...@m5sim.org > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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