Joe, This should fix the bugs you found with the three-level cache config and the recent patches. I also tried to reproduce your problems with the prefetcher but couldn't, though I was using the default fixed-latency memory model so that could be a factor. Let me know where things stand for you.
Steve On Thu, Jul 8, 2010 at 5:55 PM, Steve Reinhardt <[email protected]> wrote: > changeset aab017d1adc6 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=aab017d1adc6 > description: > cache: fix bug in SC upgrade handling > This bug was introduced with the recent rework of SC > failure handling in cset f97b62be544f. > > diffstat: > > src/mem/cache/cache_impl.hh | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diffs (12 lines): > > diff -r 10510cc7bb9f -r aab017d1adc6 src/mem/cache/cache_impl.hh > --- a/src/mem/cache/cache_impl.hh Thu Jul 08 16:18:20 2010 -0700 > +++ b/src/mem/cache/cache_impl.hh Thu Jul 08 17:56:13 2010 -0700 > @@ -1347,6 +1347,8 @@ > // as if we got a failure response > pkt = new Packet(tgt_pkt); > pkt->cmd = MemCmd::UpgradeFailResp; > + pkt->senderState = mshr; > + pkt->firstWordTime = pkt->finishTime = curTick; > handleResponse(pkt); > return NULL; > } else if (mshr->isForwardNoResponse()) { > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
