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Is the root problem here that when I have an A<->B port connection, then I connect A to C, B still thinks it's connected to A even though it's not? (Where in this specific example, A is the cache, and B and C are different CPUs.) If so, I'd rather see a more general solution like having Port::setPeer() automatically clear out any previous peer's pointer back to itself. I would not be terribly surprised if this had surprising and ugly ramifications and we run away scared, but I'd at least like to try that before going with a localized workaround like this. Does that make sense? Can you give it a try? - Steve On 2010-07-09 18:12:36, Timothy Jones wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/49/ > ----------------------------------------------------------- > > (Updated 2010-07-09 18:12:36) > > > Review request for Default. > > > Summary > ------- > > Sim: When one CPU is taking over from another, the new CPU's memory is only > connected up if it's not connected to something already. However, when > sharing caches between several CPUs and repeatedly switching between them, > the CPU thinks it is connected up when it actually isn't. To rectify this, > provide a new parameter to the takeOverFrom function that forces memory > to be connected up. > > > Diffs > ----- > > src/cpu/base.hh 249f174e6f37 > src/cpu/base.cc 249f174e6f37 > src/cpu/checker/cpu.hh 249f174e6f37 > src/cpu/checker/cpu_impl.hh 249f174e6f37 > src/cpu/o3/cpu.hh 249f174e6f37 > src/cpu/o3/cpu.cc 249f174e6f37 > src/cpu/simple/atomic.hh 249f174e6f37 > src/cpu/simple/atomic.cc 249f174e6f37 > src/cpu/simple/timing.hh 249f174e6f37 > src/cpu/simple/timing.cc 249f174e6f37 > src/python/m5/SimObject.py 249f174e6f37 > src/python/m5/simulate.py 249f174e6f37 > src/python/swig/sim_object.i 249f174e6f37 > src/sim/sim_object.hh 249f174e6f37 > src/sim/sim_object.cc 249f174e6f37 > > Diff: http://reviews.m5sim.org/r/49/diff > > > Testing > ------- > > > Thanks, > > Timothy > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
