Hi, I am simulating a 3-level cache hierarchy (private L1 and L2, shared L3) which has variable read and write latencies. I modified the files in m5's src/mem/cache directory and wherever latency was getting added to the timer tick, I check if the request is a write request. The code looks like this:
time = curTick + latency; is modified as if (pkt->isWrite()) time = curTick + writeHitlatency; else time = curTick + latency; I'm trying to measure the sensitivity of write latencies to the performance of PARSEC workloads. Since M5 supports PARSEC in full-system mode, I'm running m5 in FS mode (using the binaries and scripts provided by UT-Austin) and use checkpointing for faster simulation. However, most PARSEC workloads segfault for input sizes larger than simdev (they run fine for test and simdev) after simulating for close to an hour. I will share the stack trace of the simulation, but before that I wanted to get a few questions cleared. Btw, I use the latest m5 code repository. My questions are as follows: *) Is it possible to simulate a cache with variable read and write latencies or are there any intricacies in the m5 codebase that stops us from simulating such a cache? If it is possible, is the code snippet above the correct way of simulating such a cache or are there any special cases that should be handled correctly for the code to work? *) I'm currently using 12 clock cycle write latency for L1-I and L1-D cache (the read latency is 1 and 3 clock cycles for L1-I and L1-D cache) and 30 cycle write latency for an L2 cache (read is 20 clock cycles). Does these values matter or would m5 take care of simulating these high latency writes correctly? *) Has anyone already tried simulating caches which have variable read and write latencies? If so, have you encountered any problems or issues that should be addressed? Any pointers on solving this will be highly appreciated. Thanks a lot. -- Bhushan
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