changeset a75564db03c3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a75564db03c3
description:
Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
diffstat:
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py | 16 ++++++------
1 files changed, 8 insertions(+), 8 deletions(-)
diffs (43 lines):
diff -r b543b8e5fcbc -r a75564db03c3
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py Sat Jul
17 08:56:49 2010 -0700
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py Wed Jul
21 09:55:57 2010 -0700
@@ -50,31 +50,31 @@
def macroop XCHG_R_M
{
- ldst t1, seg, sib, disp
- st reg, seg, sib, disp
+ ldstl t1, seg, sib, disp
+ stul reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
- ldst t1, seg, riprel, disp
- st reg, seg, riprel, disp
+ ldstl t1, seg, riprel, disp
+ stul reg, seg, riprel, disp
mov reg, reg, t1
};
def macroop XCHG_M_R
{
- ldst t1, seg, sib, disp
- st reg, seg, sib, disp
+ ldstl t1, seg, sib, disp
+ stul reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
- ldst t1, seg, riprel, disp
- st reg, seg, riprel, disp
+ ldstl t1, seg, riprel, disp
+ stul reg, seg, riprel, disp
mov reg, reg, t1
};
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