changeset a3a439363a47 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a3a439363a47 description: ARM: Add regression tests
diffstat: tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/00.gzip/ref/arm/linux/simple-atomic/simout | 46 + tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/00.gzip/ref/arm/linux/simple-timing/simerr | 3 + tests/long/00.gzip/ref/arm/linux/simple-timing/simout | 46 + tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/10.mcf/ref/arm/linux/simple-atomic/simout | 31 + tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/10.mcf/ref/arm/linux/simple-timing/simerr | 3 + tests/long/10.mcf/ref/arm/linux/simple-timing/simout | 31 + tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/20.parser/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/20.parser/ref/arm/linux/simple-atomic/simout | 75 + tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/20.parser/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/20.parser/ref/arm/linux/simple-timing/simerr | 3 + tests/long/20.parser/ref/arm/linux/simple-timing/simout | 75 + tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/30.eon/ref/arm/linux/simple-atomic/simerr | 49 + tests/long/30.eon/ref/arm/linux/simple-atomic/simout | 21 + tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/30.eon/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/30.eon/ref/arm/linux/simple-timing/simerr | 49 + tests/long/30.eon/ref/arm/linux/simple-timing/simout | 21 + tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr | 5 + tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout | 1393 ++++++++++ tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr | 5 + tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout | 1393 ++++++++++ tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/50.vortex/ref/arm/linux/simple-atomic/simout | 16 + tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/50.vortex/ref/arm/linux/simple-timing/simerr | 3 + tests/long/50.vortex/ref/arm/linux/simple-timing/simout | 16 + tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout | 32 + tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr | 3 + tests/long/60.bzip2/ref/arm/linux/simple-timing/simout | 32 + tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 233 + tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini | 90 + tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr | 3 + tests/long/70.twolf/ref/arm/linux/simple-atomic/simout | 31 + tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt | 36 + tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini | 190 + tests/long/70.twolf/ref/arm/linux/simple-timing/simerr | 3 + tests/long/70.twolf/ref/arm/linux/simple-timing/simout | 31 + tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt | 233 + 64 files changed, 7826 insertions(+), 0 deletions(-) diffs (truncated from 8082 to 300 lines): diff -r ffac9df60637 -r a3a439363a47 tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini Tue Jul 27 01:03:44 2010 -0400 @@ -0,0 +1,90 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.itb] +type=ArmTLB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[0] + diff -r ffac9df60637 -r a3a439363a47 tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr Tue Jul 27 01:03:44 2010 -0400 @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff -r ffac9df60637 -r a3a439363a47 tests/long/00.gzip/ref/arm/linux/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/simout Tue Jul 27 01:03:44 2010 -0400 @@ -0,0 +1,46 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Jul 25 2010 20:52:35 +M5 revision ffac9df60637 7512 default tip +M5 started Jul 26 2010 23:53:12 +M5 executing on zizzer +command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 298674141000 because target called exit() diff -r ffac9df60637 -r a3a439363a47 tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt Tue Jul 27 01:03:44 2010 -0400 @@ -0,0 +1,36 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 2670640 # Simulator instruction rate (inst/s) +host_mem_usage 197140 # Number of bytes of host memory used +host_seconds 223.66 # Real time elapsed on the host +host_tick_rate 1335369827 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 597325393 # Number of instructions simulated +sim_seconds 0.298674 # Number of seconds simulated +sim_ticks 298674141000 # Number of ticks simulated +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 597348283 # number of cpu cycles simulated +system.cpu.num_insts 597325393 # Number of instructions executed +system.cpu.num_refs 219174038 # Number of memory references +system.cpu.workload.PROG:num_syscalls 48 # Number of system calls + +---------- End Simulation Statistics ---------- diff -r ffac9df60637 -r a3a439363a47 tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini Tue Jul 27 01:03:44 2010 -0400 @@ -0,0 +1,190 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=ArmTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=ArmTLB _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
