changeset cfbbc9178e7a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cfbbc9178e7a
description:
TimingSimpleCPU: fix NO_ACCESS memory op handling
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op
doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs
to handle the case where the current status of the CPU is Running
and not DcacheWaitResponse or DTBWaitResponse
diffstat:
src/cpu/simple/timing.cc | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (20 lines):
diff -r 82453f1b46c5 -r cfbbc9178e7a src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Sun Aug 08 22:57:16 2010 -0700
+++ b/src/cpu/simple/timing.cc Thu Aug 12 17:16:02 2010 -0700
@@ -868,6 +868,8 @@
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt->isError());
+ assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+ pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@@ -897,7 +899,6 @@
}
}
- assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
_status = Running;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
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