changeset 917208416d2a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=917208416d2a
description:
CPU: Tidy up endianness handling for mmapped "IPR"s.
diffstat:
src/arch/sparc/tlb.cc | 2 +-
src/cpu/simple/atomic.cc | 6 ++----
2 files changed, 3 insertions(+), 5 deletions(-)
diffs (35 lines):
diff -r 82453f1b46c5 -r 917208416d2a src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Sun Aug 08 22:57:16 2010 -0700
+++ b/src/arch/sparc/tlb.cc Fri Aug 13 06:10:45 2010 -0700
@@ -1049,7 +1049,7 @@
Tick
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
- uint64_t data = gtoh(pkt->get<uint64_t>());
+ uint64_t data = pkt->get<uint64_t>();
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();
diff -r 82453f1b46c5 -r 917208416d2a src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sun Aug 08 22:57:16 2010 -0700
+++ b/src/cpu/simple/atomic.cc Fri Aug 13 06:10:45 2010 -0700
@@ -450,6 +450,8 @@
traceData->setData(data);
}
+ data = htog(data);
+
//The block size of our peer.
unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
@@ -496,10 +498,6 @@
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
- //XXX This needs to be outside of the loop in order to
- //work properly for cache line boundary crossing
- //accesses in transendian simulations.
- data = htog(data);
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
dcache_latency += physmemPort.sendAtomic(&pkt);
else
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