changeset 67c670459d01 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=67c670459d01 description: CPU: Add readBytes and writeBytes functions to the exec contexts.
diffstat: src/cpu/base_dyn_inst.hh | 57 ++++++++-- src/cpu/exec_context.hh | 5 + src/cpu/inorder/cpu.cc | 122 +--------------------- src/cpu/inorder/cpu.hh | 9 +- src/cpu/inorder/inorder_dyn_inst.cc | 35 +++++- src/cpu/inorder/inorder_dyn_inst.hh | 7 +- src/cpu/inorder/resources/cache_unit.cc | 170 +++++-------------------------- src/cpu/inorder/resources/cache_unit.hh | 9 +- src/cpu/o3/cpu.hh | 6 +- src/cpu/o3/lsq.hh | 12 +- src/cpu/o3/lsq_unit.hh | 27 ++-- src/cpu/simple/atomic.cc | 86 ++++++++++------ src/cpu/simple/atomic.hh | 5 + src/cpu/simple/timing.cc | 59 +++++++--- src/cpu/simple/timing.hh | 10 + 15 files changed, 253 insertions(+), 366 deletions(-) diffs (truncated from 1270 to 300 lines): diff -r 28f052c55332 -r 67c670459d01 src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh Fri Aug 13 06:16:00 2010 -0700 +++ b/src/cpu/base_dyn_inst.hh Fri Aug 13 06:16:02 2010 -0700 @@ -120,6 +120,8 @@ template <class T> Fault read(Addr addr, T &data, unsigned flags); + Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); + /** * Does a write to a given address. * @param data The data to be written. @@ -131,6 +133,9 @@ template <class T> Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault writeBytes(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res); + /** Splits a request in two if it crosses a dcache block. */ void splitRequest(RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh); @@ -867,12 +872,12 @@ }; template<class Impl> -template<class T> -inline Fault -BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) +Fault +BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, + unsigned size, unsigned flags) { reqMade = true; - Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + Request *req = new Request(asid, addr, size, flags, this->PC, thread->contextId(), threadNumber); Request *sreqLow = NULL; @@ -889,11 +894,6 @@ effAddrValid = true; fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); } else { - - // Return a fixed value to keep simulation deterministic even - // along misspeculated paths. - data = (T)-1; - // Commit will have to clean up whatever happened. Set this // instruction as executed. this->setExecuted(); @@ -901,7 +901,6 @@ if (traceData) { traceData->setAddr(addr); - traceData->setData(data); } return fault; @@ -910,15 +909,35 @@ template<class Impl> template<class T> inline Fault -BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) +BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) +{ + Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); + + if (fault != NoFault) { + // Return a fixed value to keep simulation deterministic even + // along misspeculated paths. + data = (T)-1; + } + data = TheISA::gtoh(data); + + if (traceData) { + traceData->setData(data); + } + + return fault; +} + +template<class Impl> +Fault +BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res) { if (traceData) { traceData->setAddr(addr); - traceData->setData(data); } reqMade = true; - Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, + Request *req = new Request(asid, addr, size, flags, this->PC, thread->contextId(), threadNumber); Request *sreqLow = NULL; @@ -940,6 +959,18 @@ } template<class Impl> +template<class T> +inline Fault +BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) +{ + if (traceData) { + traceData->setData(data); + } + data = TheISA::htog(data); + return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); +} + +template<class Impl> inline void BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, RequestPtr &sreqHigh) diff -r 28f052c55332 -r 67c670459d01 src/cpu/exec_context.hh --- a/src/cpu/exec_context.hh Fri Aug 13 06:16:00 2010 -0700 +++ b/src/cpu/exec_context.hh Fri Aug 13 06:16:02 2010 -0700 @@ -111,12 +111,17 @@ template <class T> Fault read(Addr addr, T &data, unsigned flags); + Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); + /** Writes to an address, creating a memory request with the given * flags. Writes data to memory. For store conditionals, returns * the result of the store in res. */ template <class T> Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault writeBytes(uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *res); + /** Prefetches an address, creating a memory request with the * given flags. */ void prefetch(Addr addr, unsigned flags); diff -r 28f052c55332 -r 67c670459d01 src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.cc Fri Aug 13 06:16:00 2010 -0700 +++ b/src/cpu/inorder/cpu.cc Fri Aug 13 06:16:02 2010 -0700 @@ -1518,135 +1518,25 @@ return dtb_res->tlb(); } -template <class T> Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, T &data, unsigned flags) +InOrderCPU::read(DynInstPtr inst, Addr addr, + uint8_t *data, unsigned size, unsigned flags) { //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case // you want to run w/out caches? CacheUnit *cache_res = dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx)); - return cache_res->read(inst, addr, data, flags); + return cache_res->read(inst, addr, data, size, flags); } -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -template Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, Twin32_t &data, unsigned flags); - -template -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, Twin64_t &data, unsigned flags); - -template -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, uint64_t &data, unsigned flags); - -template -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, uint32_t &data, unsigned flags); - -template -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, uint16_t &data, unsigned flags); - -template -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, uint8_t &data, unsigned flags); - -#endif //DOXYGEN_SHOULD_SKIP_THIS - -template<> -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, double &data, unsigned flags) -{ - return read(inst, addr, *(uint64_t*)&data, flags); -} - -template<> -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, float &data, unsigned flags) -{ - return read(inst, addr, *(uint32_t*)&data, flags); -} - - -template<> -Fault -InOrderCPU::read(DynInstPtr inst, Addr addr, int32_t &data, unsigned flags) -{ - return read(inst, addr, (uint32_t&)data, flags); -} - -template <class T> -Fault -InOrderCPU::write(DynInstPtr inst, T data, Addr addr, unsigned flags, - uint64_t *write_res) +InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size, + Addr addr, unsigned flags, uint64_t *write_res) { //@TODO: Generalize name "CacheUnit" to "MemUnit" just in case // you want to run w/out caches? CacheUnit *cache_res = dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx)); - return cache_res->write(inst, data, addr, flags, write_res); + return cache_res->write(inst, data, size, addr, flags, write_res); } - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -template -Fault -InOrderCPU::write(DynInstPtr inst, Twin32_t data, Addr addr, - unsigned flags, uint64_t *res); - -template -Fault -InOrderCPU::write(DynInstPtr inst, Twin64_t data, Addr addr, - unsigned flags, uint64_t *res); - -template -Fault -InOrderCPU::write(DynInstPtr inst, uint64_t data, Addr addr, - unsigned flags, uint64_t *res); - -template -Fault -InOrderCPU::write(DynInstPtr inst, uint32_t data, Addr addr, - unsigned flags, uint64_t *res); - -template -Fault -InOrderCPU::write(DynInstPtr inst, uint16_t data, Addr addr, - unsigned flags, uint64_t *res); - -template -Fault -InOrderCPU::write(DynInstPtr inst, uint8_t data, Addr addr, - unsigned flags, uint64_t *res); - -#endif //DOXYGEN_SHOULD_SKIP_THIS - -template<> -Fault -InOrderCPU::write(DynInstPtr inst, double data, Addr addr, unsigned flags, - uint64_t *res) -{ - return write(inst, *(uint64_t*)&data, addr, flags, res); -} - -template<> -Fault -InOrderCPU::write(DynInstPtr inst, float data, Addr addr, unsigned flags, - uint64_t *res) -{ - return write(inst, *(uint32_t*)&data, addr, flags, res); -} - - -template<> -Fault -InOrderCPU::write(DynInstPtr inst, int32_t data, Addr addr, unsigned flags, - uint64_t *res) -{ - return write(inst, (uint32_t)data, addr, flags, res); -} diff -r 28f052c55332 -r 67c670459d01 src/cpu/inorder/cpu.hh --- a/src/cpu/inorder/cpu.hh Fri Aug 13 06:16:00 2010 -0700 +++ b/src/cpu/inorder/cpu.hh Fri Aug 13 06:16:02 2010 -0700 @@ -523,15 +523,14 @@ /** Forwards an instruction read to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") */ - template <class T> - Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags); + Fault read(DynInstPtr inst, Addr addr, + uint8_t *data, unsigned size, unsigned flags); /** Forwards an instruction write. to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") */ - template <class T> - Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags, _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev