changeset 42da07116e12 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=42da07116e12
description:
ruby: Converted old ruby debug calls to M5 debug calls
This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
diffstat:
src/cpu/testers/rubytest/CheckTable.cc | 3 +-
src/mem/SConscript | 16 ++-
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 26 ++--
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 32 ++---
src/mem/protocol/MESI_CMP_directory-dir.sm | 20 +-
src/mem/protocol/MI_example-cache.sm | 8 +-
src/mem/protocol/MI_example-dir.sm | 12 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 19 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 40 +++---
src/mem/protocol/MOESI_CMP_directory-dir.sm | 16 +-
src/mem/protocol/MOESI_CMP_directory-perfectDir.sm | 4 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 36 +++---
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 8 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 22 +-
src/mem/protocol/MOESI_hammer-cache.sm | 26 ++--
src/mem/protocol/MOESI_hammer-dir.sm | 40 +++---
src/mem/ruby/SConsopts | 3 +-
src/mem/ruby/buffers/MessageBuffer.cc | 47
+++-----
src/mem/ruby/common/Debug.cc | 7 -
src/mem/ruby/common/Debug.hh | 57
----------
src/mem/ruby/common/NetDest.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 5 +-
src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc | 4 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 5 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc | 4 +-
src/mem/ruby/network/simple/PerfectSwitch.cc | 31 ++---
src/mem/ruby/network/simple/Throttle.cc | 19 +--
src/mem/ruby/network/simple/Topology.cc | 12 +-
src/mem/ruby/storebuffer/storebuffer.cc | 46 +------
src/mem/ruby/system/CacheMemory.cc | 14 +-
src/mem/ruby/system/DirectoryMemory.cc | 2 +-
src/mem/ruby/system/SConscript | 3 -
src/mem/ruby/system/SparseMemory.cc | 31 ++--
src/mem/ruby/tester/RaceyPseudoThread.cc | 4 +-
src/mem/slicc/ast/FuncCallExprAST.py | 32 ++++-
src/mem/slicc/symbols/StateMachine.py | 22 +--
36 files changed, 284 insertions(+), 394 deletions(-)
diffs (truncated from 1942 to 300 lines):
diff -r 2b5fbdcbfb5d -r 42da07116e12 src/cpu/testers/rubytest/CheckTable.cc
--- a/src/cpu/testers/rubytest/CheckTable.cc Fri Nov 26 20:47:23 2010 -0500
+++ b/src/cpu/testers/rubytest/CheckTable.cc Wed Dec 01 11:30:04 2010 -0800
@@ -111,8 +111,7 @@
Check*
CheckTable::getCheck(const Address& address)
{
- DEBUG_MSG(TESTER_COMP, MedPrio, "Looking for check by address");
- DEBUG_EXPR(TESTER_COMP, MedPrio, address);
+ DPRINTF(RubyTest, "Looking for check by address: %s", address);
m5::hash_map<Address, Check*>::iterator i = m_lookup_map.find(address);
diff -r 2b5fbdcbfb5d -r 42da07116e12 src/mem/SConscript
--- a/src/mem/SConscript Fri Nov 26 20:47:23 2010 -0500
+++ b/src/mem/SConscript Wed Dec 01 11:30:04 2010 -0800
@@ -59,4 +59,18 @@
TraceFlag('LLSC')
TraceFlag('MMU')
TraceFlag('MemoryAccess')
-TraceFlag('Ruby')
+
+TraceFlag('RubyCache')
+TraceFlag('RubyDma')
+TraceFlag('RubyGenerated')
+TraceFlag('RubyMemory')
+TraceFlag('RubyNetwork')
+TraceFlag('RubyQueue')
+TraceFlag('RubyPort')
+TraceFlag('RubySlicc')
+TraceFlag('RubyStorebuffer')
+TraceFlag('RubyTester')
+
+CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
+ 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache',
+ 'RubyMemory', 'RubyDma'])
diff -r 2b5fbdcbfb5d -r 42da07116e12
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Fri Nov 26 20:47:23
2010 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Wed Dec 01 11:30:04
2010 -0800
@@ -329,8 +329,8 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
- DEBUG_EXPR(address);
- //DEBUG_EXPR(out_msg.Destination);
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
@@ -346,8 +346,8 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
- DEBUG_EXPR(address);
- //DEBUG_EXPR(out_msg.Destination);
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
@@ -362,11 +362,11 @@
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
- //DEBUG_EXPR(machineID);
+ DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
- DEBUG_EXPR(address);
- //DEBUG_EXPR(out_msg.Destination);
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
@@ -382,8 +382,8 @@
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
- DEBUG_EXPR(address);
- //DEBUG_EXPR(out_msg.Destination);
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
@@ -522,7 +522,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DEBUG_EXPR(address);
+ DPRINTF(RubySlicc, "%s\n", address);
}
}
@@ -535,7 +535,7 @@
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit,
l2_select_num_bits));
out_msg.MessageSize := MessageSizeType:Response_Control;
- DEBUG_EXPR(address);
+ DPRINTF(RubySlicc, "%s\n", address);
}
}
@@ -543,12 +543,12 @@
action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load
completed.") {
- //DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
+ DPRINTF(RubySlicc, "%s\n", getL1CacheEntry(address).DataBlk);
sequencer.readCallback(address, getL1CacheEntry(address).DataBlk);
}
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that
store completed.") {
- //DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
+ DPRINTF(RubySlicc, "%s\n", getL1CacheEntry(address).DataBlk);
sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk);
getL1CacheEntry(address).Dirty := true;
}
diff -r 2b5fbdcbfb5d -r 42da07116e12
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Fri Nov 26 20:47:23
2010 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Wed Dec 01 11:30:04
2010 -0800
@@ -188,9 +188,8 @@
}
void addSharer(Address addr, MachineID requestor) {
- //DEBUG_EXPR(machineID);
- //DEBUG_EXPR(requestor);
- //DEBUG_EXPR(addr);
+ DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+ machineID, requestor, addr);
getL2CacheEntry(addr).Sharers.add(requestor);
}
@@ -251,8 +250,7 @@
return Event:L1_PUTX_old;
}
} else {
- DEBUG_EXPR(addr);
- DEBUG_EXPR(type);
+ DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
error("Invalid L1 forwarded request type");
}
}
@@ -267,11 +265,9 @@
in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache) {
if(L1unblockNetwork_in.isReady()) {
peek(L1unblockNetwork_in, ResponseMsg) {
- DEBUG_EXPR(in_msg.Address);
- DEBUG_EXPR(getState(in_msg.Address));
- DEBUG_EXPR(in_msg.Sender);
- DEBUG_EXPR(in_msg.Type);
- DEBUG_EXPR(in_msg.Destination);
+ DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
+ in_msg.Address, getState(in_msg.Address), in_msg.Sender,
+ in_msg.Type, in_msg.Destination);
assert(in_msg.Destination.isElement(machineID));
if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
@@ -329,12 +325,9 @@
in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache) {
if(L1RequestIntraChipL2Network_in.isReady()) {
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- DEBUG_EXPR(in_msg.Address);
- //DEBUG_EXPR(id);
- DEBUG_EXPR(getState(in_msg.Address));
- //DEBUG_EXPR(in_msg.Requestor);
- DEBUG_EXPR(in_msg.Type);
- //DEBUG_EXPR(in_msg.Destination);
+ DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
+ in_msg.Address, getState(in_msg.Address), in_msg.Requestor,
+ in_msg.Type, in_msg.Destination);
assert(machineIDToMachineType(in_msg.Requestor) ==
MachineType:L1Cache);
assert(in_msg.Destination.isElement(machineID));
if (L2cacheMemory.isTagPresent(in_msg.Address)) {
@@ -506,12 +499,11 @@
out_msg.Type := CoherenceResponseType:DATA;
out_msg.Sender := machineID;
out_msg.Destination.add(L2_TBEs[address].L1_GetX_ID);
- //DEBUG_EXPR(out_msg.Destination);
+ DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := getL2CacheEntry(address).DataBlk;
out_msg.Dirty := getL2CacheEntry(address).Dirty;
- DEBUG_EXPR(out_msg.Address);
- //DEBUG_EXPR(out_msg.Destination);
- //DEBUG_EXPR(out_msg.DataBlk);
+ DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
+ out_msg.Address, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
diff -r 2b5fbdcbfb5d -r 42da07116e12 src/mem/protocol/MESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm Fri Nov 26 20:47:23
2010 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm Wed Dec 01 11:30:04
2010 -0800
@@ -167,7 +167,7 @@
} else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address));
} else {
- DEBUG_EXPR(in_msg);
+ DPRINTF(RubySlicc, "%s\n", in_msg);
error("Invalid message");
}
}
@@ -183,7 +183,7 @@
} else if (in_msg.Type == CoherenceResponseType:ACK) {
trigger(Event:CleanReplacement, in_msg.Address);
} else {
- DEBUG_EXPR(in_msg.Type);
+ DPRINTF(RubySlicc, "%s\n", in_msg.Type);
error("Invalid message");
}
}
@@ -199,7 +199,7 @@
} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
trigger(Event:Memory_Ack, in_msg.Address);
} else {
- DEBUG_EXPR(in_msg.Type);
+ DPRINTF(RubySlicc, "%s\n", in_msg.Type);
error("Invalid message");
}
}
@@ -271,7 +271,7 @@
out_msg.Prefetch := in_msg.Prefetch;
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
- DEBUG_EXPR(out_msg);
+ DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
}
@@ -287,7 +287,7 @@
out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch;
- DEBUG_EXPR(out_msg);
+ DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
}
@@ -295,8 +295,8 @@
action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
peek(responseNetwork_in, ResponseMsg) {
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
- DEBUG_EXPR(in_msg.Address);
- DEBUG_EXPR(in_msg.DataBlk);
+ DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ in_msg.Address, in_msg.DataBlk);
}
}
//added by SS for dma
@@ -309,7 +309,7 @@
out_msg.OriginalRequestorMachId := machineID;
out_msg.MessageSize := in_msg.MessageSize;
out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
- DEBUG_EXPR(out_msg);
+ DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
}
@@ -349,7 +349,7 @@
out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch;
- DEBUG_EXPR(out_msg);
+ DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
}
@@ -439,7 +439,7 @@
out_msg.MessageSize := in_msg.MessageSize;
//out_msg.Prefetch := in_msg.Prefetch;
- DEBUG_EXPR(out_msg);
+ DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
}
diff -r 2b5fbdcbfb5d -r 42da07116e12 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Fri Nov 26 20:47:23 2010 -0500
+++ b/src/mem/protocol/MI_example-cache.sm Wed Dec 01 11:30:04 2010 -0800
@@ -273,7 +273,7 @@
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
- DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
sequencer.readCallback(address,
GenericMachineType:L1Cache,
getCacheEntry(address).DataBlk);
@@ -281,7 +281,7 @@
action(rx_load_hit, "rx", desc="External load completed.") {
peek(responseNetwork_in, ResponseMsg) {
- DEBUG_EXPR(getCacheEntry(address).DataBlk);
+ DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
sequencer.readCallback(address,
getNondirectHitMachType(in_msg.Sender),
getCacheEntry(address).DataBlk);
@@ -289,7 +289,7 @@
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