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I think we talked about this already, but I think the changes to O3 here are fixing a problem that's really in the ARM predecoder. It should make sure it doesn't call consumeBytes with more bytes than are actually there to consume (and avoid triggering the assert there). Instead, this change seems to force O3 to always provide a maximal number of bytes to the predecoder. I'd also really want this tested with x86 before it's committed since x86's instruction length is a little more adventuresome than ARM's. I sent a patch to you at some point that would get the x86 spec regressions to run on O3, but I'm not sure when or whether you'll be able to find it easily. If you need it again I'll try to dig it up. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/341/#comment766> Brace goes on the same line as the if, else on the same line as the closing brace. - Gabe On 2010-12-06 16:12:00, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/341/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:00) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. > > > Diffs > ----- > > src/arch/arm/predecoder.hh 2b5fbdcbfb5d > src/arch/arm/predecoder.cc 2b5fbdcbfb5d > src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/341/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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