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The first line of the commit message needs to be the summary line. I really disagree with this change. It's a performance optimization that's really only useful in one ISA, and it's likely going to impact the performance of all ISAs, possibly to the point of being a wash or actually slowing things down with ARM. Have you measured what the performance impact is in ARM and, say, X86_SE? src/arch/arm/predecoder.hh <http://reviews.m5sim.org/r/344/#comment778> small d src/cpu/simple/base.cc <http://reviews.m5sim.org/r/344/#comment779> The braces are wrong. Have you tried this with x86? X86_FS? This looks like it will reset the predecoder constantly because the pcState is advanced but thread->pcState is not. I don't see how this is the right thing to do if it's not assumed that predecoder state (ITSTATE) needs to be updated when branching. - Gabe On 2010-12-06 16:12:58, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/344/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:12:58) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > The CPSR register should only be used for collecting the itstate when the > pipeline is flushed (e.g. init/reset/control flushes). > > > Diffs > ----- > > src/arch/arm/predecoder.hh 2b5fbdcbfb5d > src/arch/arm/predecoder.cc 2b5fbdcbfb5d > src/cpu/simple/base.cc 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/344/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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