changeset a8fc35183c10 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a8fc35183c10
description:
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} //
namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh
files
and src/SConscript.
diffstat:
src/SConscript | 4 ++--
src/arch/alpha/mt.hh | 2 +-
src/arch/alpha/pagetable.cc | 2 +-
src/arch/alpha/tlb.cc | 2 +-
src/arch/arm/faults.hh | 2 +-
src/arch/arm/isa_traits.hh | 4 ++--
src/arch/arm/kernel_stats.hh | 4 ++--
src/arch/arm/nativetrace.cc | 2 +-
src/arch/arm/nativetrace.hh | 2 +-
src/arch/arm/tlb.hh | 2 +-
src/arch/mips/dsp.hh | 2 +-
src/arch/mips/faults.hh | 2 +-
src/arch/mips/isa_traits.hh | 4 ++--
src/arch/mips/kernel_stats.hh | 4 ++--
src/arch/mips/linux/threadinfo.hh | 2 +-
src/arch/power/faults.hh | 2 +-
src/arch/power/insts/branch.hh | 2 +-
src/arch/power/insts/condition.hh | 2 +-
src/arch/power/insts/floating.hh | 2 +-
src/arch/power/insts/integer.hh | 2 +-
src/arch/power/insts/mem.hh | 2 +-
src/arch/power/insts/misc.hh | 2 +-
src/arch/power/insts/static_inst.hh | 2 +-
src/arch/power/isa.hh | 2 +-
src/arch/power/isa_traits.hh | 4 ++--
src/arch/power/locked_mem.hh | 2 +-
src/arch/power/microcode_rom.hh | 2 +-
src/arch/power/miscregs.hh | 2 +-
src/arch/power/mmaped_ipr.hh | 2 +-
src/arch/power/pagetable.cc | 2 +-
src/arch/power/pagetable.hh | 2 +-
src/arch/power/predecoder.hh | 2 +-
src/arch/power/registers.hh | 2 +-
src/arch/power/remote_gdb.hh | 2 +-
src/arch/power/stacktrace.hh | 2 +-
src/arch/power/tlb.hh | 2 +-
src/arch/power/types.hh | 2 +-
src/arch/power/utility.cc | 2 +-
src/arch/power/utility.hh | 2 +-
src/arch/power/vtophys.hh | 2 +-
src/arch/sparc/faults.hh | 2 +-
src/arch/sparc/kernel_stats.hh | 4 ++--
src/arch/sparc/nativetrace.cc | 2 +-
src/arch/sparc/nativetrace.hh | 2 +-
src/arch/sparc/tlb.cc | 2 +-
src/arch/sparc/vtophys.cc | 2 +-
src/arch/x86/cpuid.cc | 2 +-
src/arch/x86/nativetrace.cc | 2 +-
src/arch/x86/nativetrace.hh | 2 +-
src/arch/x86/registers.hh | 2 +-
src/arch/x86/tlb.cc | 2 +-
src/arch/x86/utility.cc | 2 +-
src/base/cprintf.cc | 2 +-
src/base/cprintf.hh | 2 +-
src/base/hashmap.hh | 2 +-
src/base/inet.cc | 2 +-
src/base/inet.hh | 2 +-
src/base/mysql.cc | 2 +-
src/base/mysql.hh | 2 +-
src/base/statistics.cc | 2 +-
src/base/statistics.hh | 2 +-
src/base/stats/info.hh | 2 +-
src/base/stats/mysql.cc | 2 +-
src/base/stats/mysql.hh | 2 +-
src/base/stats/mysql_run.hh | 2 +-
src/base/stats/output.cc | 2 +-
src/base/stats/output.hh | 2 +-
src/base/stats/text.cc | 2 +-
src/base/stats/text.hh | 2 +-
src/base/stats/types.hh | 2 +-
src/base/stats/visit.cc | 2 +-
src/base/stats/visit.hh | 2 +-
src/base/stl_helpers.hh | 4 ++--
src/base/trace.cc | 2 +-
src/base/trace.hh | 2 +-
src/base/varargs.hh | 2 +-
src/cpu/exetrace.cc | 2 +-
src/cpu/exetrace.hh | 2 +-
src/cpu/inorder/inorder_trace.cc | 2 +-
src/cpu/inorder/inorder_trace.hh | 2 +-
src/cpu/inteltrace.cc | 2 +-
src/cpu/inteltrace.hh | 2 +-
src/cpu/legiontrace.cc | 2 +-
src/cpu/legiontrace.hh | 2 +-
src/cpu/nativetrace.cc | 2 +-
src/cpu/nativetrace.hh | 2 +-
src/dev/copy_engine_defs.hh | 2 +-
src/dev/i8254xGBe_defs.hh | 2 +-
src/dev/sinic.cc | 2 +-
src/dev/sinic.hh | 2 +-
src/dev/sinicreg.hh | 4 ++--
src/dev/x86/cmos.hh | 2 +-
src/dev/x86/i8042.hh | 2 +-
src/dev/x86/i82094aa.hh | 2 +-
src/dev/x86/i8237.hh | 2 +-
src/dev/x86/i8254.hh | 2 +-
src/dev/x86/i8259.hh | 2 +-
src/dev/x86/intdev.hh | 2 +-
src/dev/x86/speaker.hh | 2 +-
src/kern/kernel_stats.cc | 2 +-
src/kern/kernel_stats.hh | 2 +-
src/mem/ruby/common/Address.hh | 4 ++--
src/python/m5/SimObject.py | 4 ++--
src/python/m5/params.py | 2 +-
src/python/swig/stats.i | 2 +-
src/sim/core.cc | 6 +++---
src/sim/core.hh | 6 +++---
src/sim/insttracer.hh | 2 +-
src/sim/pseudo_inst.cc | 2 +-
src/sim/pseudo_inst.hh | 2 +-
src/sim/stat_control.cc | 2 +-
src/sim/stat_control.hh | 2 +-
112 files changed, 127 insertions(+), 127 deletions(-)
diffs (truncated from 1309 to 300 lines):
diff -r 3a790012d6ed -r a8fc35183c10 src/SConscript
--- a/src/SConscript Mon Jan 03 15:31:20 2011 -0500
+++ b/src/SConscript Mon Jan 03 14:35:43 2011 -0800
@@ -835,7 +835,7 @@
// base flags to set. Inidividual flag arrays are terminated by -1.
extern const Flags *compoundFlags[];
-/* namespace Trace */ }
+} // namespace Trace
#endif // __BASE_TRACE_FLAGS_HH__
''')
@@ -902,7 +902,7 @@
${{len(data)}},
${{len(marshalled)}});
-/* namespace */ }
+} // anonymous namespace
''')
code.write(str(target[0]))
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/alpha/mt.hh
--- a/src/arch/alpha/mt.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/alpha/mt.hh Mon Jan 03 14:35:43 2011 -0800
@@ -66,6 +66,6 @@
return 0;
}
-}//namespace AlphaISA
+} // namespace AlphaISA
#endif
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/alpha/pagetable.cc
--- a/src/arch/alpha/pagetable.cc Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/alpha/pagetable.cc Mon Jan 03 14:35:43 2011 -0800
@@ -61,4 +61,4 @@
UNSERIALIZE_SCALAR(valid);
}
-} //namespace AlphaISA
+} // namespace AlphaISA
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/alpha/tlb.cc Mon Jan 03 14:35:43 2011 -0800
@@ -595,7 +595,7 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
-/* end namespace AlphaISA */ }
+} // namespace AlphaISA
AlphaISA::TLB *
AlphaTLBParams::create()
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/faults.hh Mon Jan 03 14:35:43 2011 -0800
@@ -246,6 +246,6 @@
return new Reset();
}
-} // ArmISA namespace
+} // namespace ArmISA
#endif // __ARM_FAULTS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/isa_traits.hh Mon Jan 03 14:35:43 2011 -0800
@@ -48,7 +48,7 @@
#include "arch/arm/types.hh"
#include "base/types.hh"
-namespace LittleEndianGuest {};
+namespace LittleEndianGuest {}
#define TARGET_ARM
@@ -123,7 +123,7 @@
INT_FIQ,
NumInterruptTypes
};
-};
+} // namespace ArmISA
using namespace ArmISA;
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/kernel_stats.hh
--- a/src/arch/arm/kernel_stats.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/kernel_stats.hh Mon Jan 03 14:35:43 2011 -0800
@@ -51,7 +51,7 @@
{}
};
-} /* end namespace ArmISA::Kernel */
-} /* end namespace ArmISA */
+} // namespace ArmISA::Kernel
+} // namespace ArmISA
#endif // __ARCH_ARM_KERNEL_STATS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/nativetrace.cc Mon Jan 03 14:35:43 2011 -0800
@@ -192,7 +192,7 @@
}
}
-} /* namespace Trace */
+} // namespace Trace
////////////////////////////////////////////////////////////////////////
//
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/nativetrace.hh
--- a/src/arch/arm/nativetrace.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/nativetrace.hh Mon Jan 03 14:35:43 2011 -0800
@@ -107,6 +107,6 @@
void check(NativeTraceRecord *record);
};
-} /* namespace Trace */
+} // namespace Trace
#endif // __ARCH_ARM_NATIVETRACE_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/arm/tlb.hh Mon Jan 03 14:35:43 2011 -0800
@@ -239,6 +239,6 @@
inline void invalidateMiscReg() { miscRegValid = false; }
};
-/* namespace ArmISA */ }
+} // namespace ArmISA
#endif // __ARCH_ARM_TLB_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/mips/dsp.hh
--- a/src/arch/mips/dsp.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/mips/dsp.hh Mon Jan 03 14:35:43 2011 -0800
@@ -199,6 +199,6 @@
void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
-} /* namespace MipsISA */
+} // namespace MipsISA
#endif // __ARCH_MIPS_DSP_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/mips/faults.hh Mon Jan 03 14:35:43 2011 -0800
@@ -596,6 +596,6 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
-} // MipsISA namespace
+} // namespace MipsISA
#endif // __MIPS_FAULTS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/mips/isa_traits.hh Mon Jan 03 14:35:43 2011 -0800
@@ -39,7 +39,7 @@
#include "base/types.hh"
#include "config/full_system.hh"
-namespace LittleEndianGuest {};
+namespace LittleEndianGuest {}
class StaticInstPtr;
@@ -164,6 +164,6 @@
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
-};
+} // namespace MipsISA
#endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/mips/kernel_stats.hh
--- a/src/arch/mips/kernel_stats.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/mips/kernel_stats.hh Mon Jan 03 14:35:43 2011 -0800
@@ -48,7 +48,7 @@
};
-} /* end namespace MipsISA::Kernel */
-} /* end namespace MipsISA */
+} // namespace MipsISA::Kernel
+} // namespace MipsISA
#endif // __ARCH_MIPS_KERNEL_STATS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/mips/linux/threadinfo.hh
--- a/src/arch/mips/linux/threadinfo.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/mips/linux/threadinfo.hh Mon Jan 03 14:35:43 2011 -0800
@@ -148,6 +148,6 @@
}
};
-/* namespace Linux */ }
+} // namespace Linux
#endif // __ARCH_MIPS_LINUX_LINUX_THREADINFO_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/faults.hh
--- a/src/arch/power/faults.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/faults.hh Mon Jan 03 14:35:43 2011 -0800
@@ -98,6 +98,6 @@
return new MachineCheckFault();
}
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_FAULTS_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/branch.hh
--- a/src/arch/power/insts/branch.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/branch.hh Mon Jan 03 14:35:43 2011 -0800
@@ -236,6 +236,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_BRANCH_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/condition.hh
--- a/src/arch/power/insts/condition.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/condition.hh Mon Jan 03 14:35:43 2011 -0800
@@ -81,6 +81,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_CONDITION_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/floating.hh
--- a/src/arch/power/insts/floating.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/floating.hh Mon Jan 03 14:35:43 2011 -0800
@@ -148,6 +148,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_FLOATING_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/integer.hh
--- a/src/arch/power/insts/integer.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/integer.hh Mon Jan 03 14:35:43 2011 -0800
@@ -171,6 +171,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_INTEGER_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/mem.hh
--- a/src/arch/power/insts/mem.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/mem.hh Mon Jan 03 14:35:43 2011 -0800
@@ -86,6 +86,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MEM_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/misc.hh
--- a/src/arch/power/insts/misc.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/misc.hh Mon Jan 03 14:35:43 2011 -0800
@@ -52,6 +52,6 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_MISC_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/insts/static_inst.hh
--- a/src/arch/power/insts/static_inst.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/insts/static_inst.hh Mon Jan 03 14:35:43 2011 -0800
@@ -71,6 +71,6 @@
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif //__ARCH_POWER_INSTS_STATICINST_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/isa.hh
--- a/src/arch/power/isa.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/isa.hh Mon Jan 03 14:35:43 2011 -0800
@@ -110,6 +110,6 @@
}
};
-} // PowerISA namespace
+} // namespace PowerISA
#endif // __ARCH_POWER_ISA_HH__
diff -r 3a790012d6ed -r a8fc35183c10 src/arch/power/isa_traits.hh
--- a/src/arch/power/isa_traits.hh Mon Jan 03 15:31:20 2011 -0500
+++ b/src/arch/power/isa_traits.hh Mon Jan 03 14:35:43 2011 -0800
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