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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. Diffs ----- src/arch/alpha/isa/decoder.isa 7338bc628489 src/arch/alpha/kernel_stats.cc 7338bc628489 src/arch/alpha/tru64/process.cc 7338bc628489 src/arch/arm/table_walker.cc 7338bc628489 src/arch/mips/isa.cc 7338bc628489 src/arch/mips/isa/formats/mt.isa 7338bc628489 src/arch/mips/locked_mem.hh 7338bc628489 src/arch/mips/mt.hh 7338bc628489 src/arch/sparc/ua2005.cc 7338bc628489 src/arch/x86/interrupts.cc 7338bc628489 src/base/cp_annotate.hh 7338bc628489 src/base/cp_annotate.cc 7338bc628489 src/base/fast_alloc.cc 7338bc628489 src/base/misc.cc 7338bc628489 src/base/remote_gdb.cc 7338bc628489 src/base/statistics.hh 7338bc628489 src/base/stats/mysql.cc 7338bc628489 src/base/stats/output.cc 7338bc628489 src/base/trace.hh 7338bc628489 src/cpu/base.hh 7338bc628489 src/cpu/base.cc 7338bc628489 src/cpu/checker/cpu.cc 7338bc628489 src/cpu/checker/cpu_impl.hh 7338bc628489 src/cpu/inorder/cpu.hh 7338bc628489 src/cpu/inorder/cpu.cc 7338bc628489 src/cpu/inorder/inorder_dyn_inst.cc 7338bc628489 src/cpu/inorder/pipeline_stage.cc 7338bc628489 src/cpu/inorder/reg_dep_map.cc 7338bc628489 src/cpu/inorder/resource.cc 7338bc628489 src/cpu/inorder/resource_pool.9stage.cc 7338bc628489 src/cpu/inorder/resource_pool.cc 7338bc628489 src/cpu/inorder/resources/branch_predictor.cc 7338bc628489 src/cpu/inorder/resources/cache_unit.cc 7338bc628489 src/cpu/inorder/resources/execution_unit.cc 7338bc628489 src/cpu/inorder/resources/fetch_seq_unit.cc 7338bc628489 src/cpu/inorder/resources/graduation_unit.cc 7338bc628489 src/cpu/inorder/resources/mult_div_unit.cc 7338bc628489 src/cpu/o3/commit_impl.hh 7338bc628489 src/cpu/o3/cpu.hh 7338bc628489 src/cpu/o3/cpu.cc 7338bc628489 src/cpu/o3/fetch_impl.hh 7338bc628489 src/cpu/o3/inst_queue_impl.hh 7338bc628489 src/cpu/o3/lsq_impl.hh 7338bc628489 src/cpu/o3/lsq_unit.hh 7338bc628489 src/cpu/o3/lsq_unit_impl.hh 7338bc628489 src/cpu/o3/thread_context_impl.hh 7338bc628489 src/cpu/ozone/back_end.hh 7338bc628489 src/cpu/ozone/cpu.hh 7338bc628489 src/cpu/ozone/cpu_impl.hh 7338bc628489 src/cpu/ozone/front_end_impl.hh 7338bc628489 src/cpu/ozone/inorder_back_end.hh 7338bc628489 src/cpu/ozone/inst_queue_impl.hh 7338bc628489 src/cpu/ozone/lsq_unit.hh 7338bc628489 src/cpu/ozone/lsq_unit_impl.hh 7338bc628489 src/cpu/ozone/lw_back_end_impl.hh 7338bc628489 src/cpu/ozone/lw_lsq.hh 7338bc628489 src/cpu/ozone/lw_lsq_impl.hh 7338bc628489 src/cpu/pc_event.cc 7338bc628489 src/cpu/simple/atomic.cc 7338bc628489 src/cpu/simple/base.cc 7338bc628489 src/cpu/simple/timing.cc 7338bc628489 src/cpu/simple_thread.cc 7338bc628489 src/cpu/static_inst.cc 7338bc628489 src/cpu/testers/directedtest/RubyDirectedTester.cc 7338bc628489 src/cpu/testers/memtest/memtest.cc 7338bc628489 src/cpu/testers/rubytest/Check.cc 7338bc628489 src/cpu/testers/rubytest/RubyTester.cc 7338bc628489 src/cpu/trace/trace_cpu.cc 7338bc628489 src/dev/alpha/backdoor.cc 7338bc628489 src/dev/arm/pl011.cc 7338bc628489 src/dev/arm/pl111.cc 7338bc628489 src/dev/arm/rv_ctrl.cc 7338bc628489 src/dev/arm/timer_sp804.cc 7338bc628489 src/dev/etherbus.cc 7338bc628489 src/dev/etherdump.cc 7338bc628489 src/dev/etherlink.cc 7338bc628489 src/dev/ethertap.cc 7338bc628489 src/dev/i8254xGBe.cc 7338bc628489 src/dev/ide_disk.cc 7338bc628489 src/dev/intel_8254_timer.cc 7338bc628489 src/dev/io_device.cc 7338bc628489 src/dev/mc146818.hh 7338bc628489 src/dev/mc146818.cc 7338bc628489 src/dev/ns_gige.cc 7338bc628489 src/dev/sinic.cc 7338bc628489 src/dev/uart8250.cc 7338bc628489 src/kern/kernel_stats.cc 7338bc628489 src/mem/bridge.cc 7338bc628489 src/mem/bus.cc 7338bc628489 src/mem/cache/base.hh 7338bc628489 src/mem/cache/base.cc 7338bc628489 src/mem/cache/blk.hh 7338bc628489 src/mem/cache/cache_impl.hh 7338bc628489 src/mem/cache/mshr.hh 7338bc628489 src/mem/cache/mshr.cc 7338bc628489 src/mem/cache/mshr_queue.hh 7338bc628489 src/mem/cache/tags/fa_lru.cc 7338bc628489 src/mem/cache/tags/iic.cc 7338bc628489 src/mem/cache/tags/lru.cc 7338bc628489 src/mem/dram.cc 7338bc628489 src/mem/mport.cc 7338bc628489 src/mem/packet.hh 7338bc628489 src/mem/request.hh 7338bc628489 src/mem/ruby/eventqueue/RubyEventQueue.hh 7338bc628489 src/mem/ruby/system/RubyPort.cc 7338bc628489 src/mem/ruby/system/Sequencer.cc 7338bc628489 src/mem/ruby/system/System.cc 7338bc628489 src/mem/tport.hh 7338bc628489 src/mem/tport.cc 7338bc628489 src/python/m5/simulate.py 7338bc628489 src/python/swig/core.i 7338bc628489 src/python/swig/stats.i 7338bc628489 src/sim/core.hh 7338bc628489 src/sim/core.cc 7338bc628489 src/sim/eventq.hh 7338bc628489 src/sim/eventq.cc 7338bc628489 src/sim/init.cc 7338bc628489 src/sim/pseudo_inst.cc 7338bc628489 src/sim/serialize.hh 7338bc628489 src/sim/serialize.cc 7338bc628489 src/sim/sim_events.cc 7338bc628489 src/sim/sim_exit.hh 7338bc628489 src/sim/sim_object.hh 7338bc628489 src/sim/simulate.cc 7338bc628489 src/sim/stat_control.hh 7338bc628489 src/sim/stat_control.cc 7338bc628489 src/sim/syscall_emul.hh 7338bc628489 src/sim/syscall_emul.cc 7338bc628489 src/unittest/stattest.cc 7338bc628489 Diff: http://reviews.m5sim.org/r/374/diff Testing ------- Thanks, Steve
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