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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- O3: Fix itstate prediction and recovery. Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details. Diffs ----- src/arch/arm/isa/insts/data.isa 5d0f62927d75 src/arch/arm/isa/insts/ldr.isa 5d0f62927d75 src/arch/arm/isa/insts/macromem.isa 5d0f62927d75 src/arch/arm/isa/insts/misc.isa 5d0f62927d75 src/arch/arm/isa/operands.isa 5d0f62927d75 src/arch/arm/predecoder.hh 5d0f62927d75 src/arch/arm/predecoder.cc 5d0f62927d75 src/arch/arm/types.hh 5d0f62927d75 Diff: http://reviews.m5sim.org/r/421/diff Testing ------- Thanks, Ali
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