----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/359/#review728 -----------------------------------------------------------
Ship it! Well Done! I have a couple questions just to clarify my understanding of what is going on, but overall this looks great to me. src/mem/protocol/MOESI_CMP_directory-L1cache.sm <http://reviews.m5sim.org/r/359/#comment992> So the assumption here is the L1IcacheMemory.lookup() call either returns the L1I cache entry or NULL/OOD, correct? Does SLICC also support explicitly passing back OOD? src/mem/protocol/MOESI_CMP_directory-L1cache.sm <http://reviews.m5sim.org/r/359/#comment993> This seems like an unrelated change, correct. However it is pretty minor, so don't worry about it. - Brad On 2011-01-12 22:44:50, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/359/ > ----------------------------------------------------------- > > (Updated 2011-01-12 22:44:50) > > > Review request for Default. > > > Summary > ------- > > This is a request for reviewing the proposed changes to the MOESI CMP > directory cache coherence protocol to make it conform with the new cache > memory interface and changes to SLICC. > > > Diffs > ----- > > src/mem/protocol/MOESI_CMP_directory-L1cache.sm c6bc8fe81e79 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm c6bc8fe81e79 > src/mem/protocol/MOESI_CMP_directory-dir.sm c6bc8fe81e79 > src/mem/protocol/MOESI_CMP_directory-dma.sm c6bc8fe81e79 > > Diff: http://reviews.m5sim.org/r/359/diff > > > Testing > ------- > > These changes have been tested using the Ruby random tester. The tester was > used with -l = 1048576 and -n = 2. > > > Thanks, > > Nilay > >
_______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev