> On 2011-01-19 07:02:40, Steve Reinhardt wrote: > > src/cpu/simple/timing.hh, line 114 > > <http://reviews.m5sim.org/r/431/diff/1/?file=9738#file9738line114> > > > > It's interesting that we already had an ITBWaitResponse state defined > > but had never used it before. Does it make sense to add an assert > > somewhere so that it's not a write-only state? That's just a random > > comment, not a deficiency in this patch.
There isn't any place where this could be tested in isolation. I think it could be assert(_status == Running || _status == ITBWaitResponse); in sendFetch(). - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/431/#review783 ----------------------------------------------------------- On 2011-01-18 14:34:11, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/431/ > ----------------------------------------------------------- > > (Updated 2011-01-18 14:34:11) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk > occurs. > > This change fixes an issue where a DTLB fault occurs and redirects fetch to > handle the fault and the ITLB requires a walk which delays translation. In > this > case the status of the cpu isn't updated appropriately, and an additional > instruction fetch occurs. Eventually this hits an assert as multiple > instruction > fetches are occuring in the system and when the second one returns the > processor is in the wrong state. > > Some asserts below are removed because it was always true (typo) and the state > after the initiateAcc() the processor could be in any valid state when a > d-side fault occurs. > > > Diffs > ----- > > src/cpu/simple/timing.hh 32b6354d2ae6 > src/cpu/simple/timing.cc 32b6354d2ae6 > > Diff: http://reviews.m5sim.org/r/431/diff > > > Testing > ------- > > > Thanks, > > Ali > >
_______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
