Hi all,
I came across some indeterminism that causes problems. Yesterday I had a bug
that workload pagetables would not unserialize if I added an l2 cache, but
would if I had only a L1 cache. The culprit appears to be
src/python/m5/simulate.py, the portion that looks for oprhans to add to
objects in the system. The problem was that the workload was getting
associated with system.switch_cpus as opposed to system.cpu, and M5 could
not find workload checkpoint information for system.switch_cpus.workload. My
fix, is given below and just puts the paths in sorted order. This however
relies on the fact that cpu occurs alphabetically before switch_cpus, which
doesn't seem like a permanent fix. The end solution would be to be able to
set a definite parent for each workload, so it is not treated like an
orphan.
Thanks,
Rick
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -58,7 +58,7 @@
# Make sure SimObject-valued params are in the configuration
# hierarchy so we catch them with future descendants() walks
- for obj in root.descendants(): obj.adoptOrphanParams()
+ for obj in sorted(root.descendants(), key=lambda o: o.path()):
obj.adoptOrphanParams()
# Unproxy in sorted order for determinism
for obj in root.descendants(): obj.unproxyParams()
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