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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- inorder: pipe. stage inst. buffering ==== Changes toward getting superscalar InOrder CPU working ==== Use skidbuffer as only location for instructions between stages. Before, we had the insts queue from the prior stage and the skidbuffer for the current stage, but that gets confusing and this consolidation helps when handling squash cases Diffs ----- src/cpu/inorder/first_stage.hh 31a04e5ac4be src/cpu/inorder/first_stage.cc 31a04e5ac4be src/cpu/inorder/pipeline_stage.hh 31a04e5ac4be src/cpu/inorder/pipeline_stage.cc 31a04e5ac4be Diff: http://reviews.m5sim.org/r/442/diff Testing ------- Thanks, Korey
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