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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. Diffs ----- configs/common/CacheConfig.py 31a04e5ac4be configs/common/Caches.py 31a04e5ac4be src/cpu/BaseCPU.py 31a04e5ac4be src/cpu/o3/O3CPU.py 31a04e5ac4be Diff: http://reviews.m5sim.org/r/454/diff Testing ------- Thanks, Gabe
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