changeset 189b9b258779 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=189b9b258779
description:
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and
uncached ports
don't conflict with each other, and that accesses which are always
uncached
(message signaled interrupts for instance) don't waste time passing
through
caches.
diffstat:
configs/common/CacheConfig.py | 4 +-
configs/example/fs.py | 2 +-
configs/splash2/run.py | 2 +-
src/cpu/BaseCPU.py | 45 +++++++++++++++------------
src/cpu/inorder/InOrderCPU.py | 2 +-
src/cpu/o3/O3CPU.py | 2 +-
src/cpu/simple/AtomicSimpleCPU.py | 4 +-
src/cpu/simple/TimingSimpleCPU.py | 2 +-
tests/configs/inorder-timing.py | 2 +-
tests/configs/o3-timing-mp-ruby.py | 2 +-
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing-ruby.py | 2 +-
tests/configs/o3-timing.py | 2 +-
tests/configs/realview-simple-atomic.py | 2 +-
tests/configs/realview-simple-timing.py | 2 +-
tests/configs/simple-atomic-mp-ruby.py | 2 +-
tests/configs/simple-atomic-mp.py | 2 +-
tests/configs/simple-atomic.py | 2 +-
tests/configs/simple-timing-mp.py | 2 +-
tests/configs/simple-timing.py | 2 +-
tests/configs/t1000-simple-atomic.py | 2 +-
tests/configs/tsunami-o3-dual.py | 2 +-
tests/configs/tsunami-o3.py | 2 +-
tests/configs/tsunami-simple-atomic-dual.py | 2 +-
tests/configs/tsunami-simple-atomic.py | 2 +-
tests/configs/tsunami-simple-timing-dual.py | 2 +-
tests/configs/tsunami-simple-timing.py | 2 +-
tests/configs/twosys-tsunami-simple-atomic.py | 4 +-
28 files changed, 55 insertions(+), 50 deletions(-)
diffs (truncated from 402 to 300 lines):
diff -r 4afd05b9485e -r 189b9b258779 configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Wed Feb 02 23:34:14 2011 -0800
+++ b/configs/common/CacheConfig.py Thu Feb 03 20:23:00 2011 -0800
@@ -52,8 +52,8 @@
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
if options.l2cache:
- system.cpu[i].connectMemPorts(system.tol2bus)
+ system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
- system.cpu[i].connectMemPorts(system.membus)
+ system.cpu[i].connectAllPorts(system.membus)
return system
diff -r 4afd05b9485e -r 189b9b258779 configs/example/fs.py
--- a/configs/example/fs.py Wed Feb 02 23:34:14 2011 -0800
+++ b/configs/example/fs.py Thu Feb 03 20:23:00 2011 -0800
@@ -178,7 +178,7 @@
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
- drive_sys.cpu.connectMemPorts(drive_sys.membus)
+ drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:
diff -r 4afd05b9485e -r 189b9b258779 configs/splash2/run.py
--- a/configs/splash2/run.py Wed Feb 02 23:34:14 2011 -0800
+++ b/configs/splash2/run.py Thu Feb 03 20:23:00 2011 -0800
@@ -218,7 +218,7 @@
cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
L1(size = options.l1size, assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2bus)
+ cpu.connectAllPorts(system.toL2bus, system.membus)
# ----------------------
diff -r 4afd05b9485e -r 189b9b258779 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Wed Feb 02 23:34:14 2011 -0800
+++ b/src/cpu/BaseCPU.py Thu Feb 03 20:23:00 2011 -0800
@@ -150,48 +150,53 @@
tracer = Param.InstTracer(default_tracer, "Instruction tracer")
- _mem_ports = []
+ _cached_ports = []
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+ _cached_ports = ["itb.walker.port", "dtb.walker.port"]
+
+ _uncached_ports = []
if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
- _mem_ports = ["itb.walker.port",
- "dtb.walker.port",
- "interrupts.pio",
- "interrupts.int_port"]
+ _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
- if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
- _mem_ports = ["itb.walker.port",
- "dtb.walker.port"]
+ def connectCachedPorts(self, bus):
+ for p in self._cached_ports:
+ exec('self.%s = bus.port' % p)
- def connectMemPorts(self, bus):
- for p in self._mem_ports:
- if p != 'physmem_port':
- exec('self.%s = bus.port' % p)
+ def connectUncachedPorts(self, bus):
+ for p in self._uncached_ports:
+ exec('self.%s = bus.port' % p)
+
+ def connectAllPorts(self, cached_bus, uncached_bus = None):
+ self.connectCachedPorts(cached_bus)
+ if not uncached_bus:
+ uncached_bus = cached_bus
+ self.connectUncachedPorts(uncached_bus)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- assert(len(self._mem_ports) < 8)
+ assert(len(self._cached_ports) < 7)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
- self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+ self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
if buildEnv['FULL_SYSTEM']:
if buildEnv['TARGET_ISA'] == 'x86':
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
self.itb.walker.port = iwc.cpu_side
self.dtb.walker.port = dwc.cpu_side
- self._mem_ports += ["itb_walker_cache.mem_side", \
- "dtb_walker_cache.mem_side"]
- self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
elif buildEnv['TARGET_ISA'] == 'arm':
- self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+ self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = Bus()
- self.connectMemPorts(self.toL2Bus)
+ self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
- self._mem_ports = ['l2cache.mem_side']
+ self._cached_ports = ['l2cache.mem_side']
if buildEnv['TARGET_ISA'] == 'mips':
CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
diff -r 4afd05b9485e -r 189b9b258779 src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Wed Feb 02 23:34:14 2011 -0800
+++ b/src/cpu/inorder/InOrderCPU.py Thu Feb 03 20:23:00 2011 -0800
@@ -46,7 +46,7 @@
dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get
data from")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
- _mem_ports = ['icache_port', 'dcache_port']
+ _cached_ports = ['icache_port', 'dcache_port']
predType = Param.String("tournament", "Branch predictor type ('local',
'tournament')")
localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
diff -r 4afd05b9485e -r 189b9b258779 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Wed Feb 02 23:34:14 2011 -0800
+++ b/src/cpu/o3/O3CPU.py Thu Feb 03 20:23:00 2011 -0800
@@ -55,7 +55,7 @@
cachePorts = Param.Unsigned(200, "Cache Ports")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
- _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
+ _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
diff -r 4afd05b9485e -r 189b9b258779 src/cpu/simple/AtomicSimpleCPU.py
--- a/src/cpu/simple/AtomicSimpleCPU.py Wed Feb 02 23:34:14 2011 -0800
+++ b/src/cpu/simple/AtomicSimpleCPU.py Thu Feb 03 20:23:00 2011 -0800
@@ -37,5 +37,5 @@
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")
- _mem_ports = BaseSimpleCPU._mem_ports + \
- ['icache_port', 'dcache_port', 'physmem_port']
+ _cached_ports = BaseSimpleCPU._cached_ports + \
+ ['icache_port', 'dcache_port']
diff -r 4afd05b9485e -r 189b9b258779 src/cpu/simple/TimingSimpleCPU.py
--- a/src/cpu/simple/TimingSimpleCPU.py Wed Feb 02 23:34:14 2011 -0800
+++ b/src/cpu/simple/TimingSimpleCPU.py Thu Feb 03 20:23:00 2011 -0800
@@ -33,4 +33,4 @@
type = 'TimingSimpleCPU'
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
- _mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
+ _cached_ports = BaseSimpleCPU._cached_ports + ['icache_port',
'dcache_port']
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/inorder-timing.py Thu Feb 03 20:23:00 2011 -0800
@@ -47,6 +47,6 @@
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/o3-timing-mp-ruby.py Thu Feb 03 20:23:00 2011 -0800
@@ -40,7 +40,7 @@
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
for cpu in cpus:
- cpu.connectMemPorts(system.membus)
+ cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/o3-timing-mp.py Thu Feb 03 20:23:00 2011 -0800
@@ -72,7 +72,7 @@
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/o3-timing-ruby.py Thu Feb 03 20:23:00 2011 -0800
@@ -41,6 +41,6 @@
physmem = ruby_memory,
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/o3-timing.py Thu Feb 03 20:23:00 2011 -0800
@@ -46,6 +46,6 @@
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
root = Root(system = system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/realview-simple-atomic.py Thu Feb 03 20:23:00 2011 -0800
@@ -88,7 +88,7 @@
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/realview-simple-timing.py Thu Feb 03 20:23:00 2011 -0800
@@ -90,7 +90,7 @@
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
-cpu.connectMemPorts(system.toL2Bus)
+cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
root = Root(system=system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/simple-atomic-mp-ruby.py
--- a/tests/configs/simple-atomic-mp-ruby.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/simple-atomic-mp-ruby.py Thu Feb 03 20:23:00 2011 -0800
@@ -41,7 +41,7 @@
# add L1 caches
for cpu in cpus:
- cpu.connectMemPorts(system.membus)
+ cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/simple-atomic-mp.py Thu Feb 03 20:23:00 2011 -0800
@@ -71,7 +71,7 @@
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/simple-atomic.py
--- a/tests/configs/simple-atomic.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/simple-atomic.py Thu Feb 03 20:23:00 2011 -0800
@@ -33,7 +33,7 @@
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-system.cpu.connectMemPorts(system.membus)
+system.cpu.connectAllPorts(system.membus)
system.cpu.clock = '2GHz'
root = Root(system = system)
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/simple-timing-mp.py Thu Feb 03 20:23:00 2011 -0800
@@ -71,7 +71,7 @@
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
- cpu.connectMemPorts(system.toL2Bus)
+ cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
diff -r 4afd05b9485e -r 189b9b258779 tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py Wed Feb 02 23:34:14 2011 -0800
+++ b/tests/configs/simple-timing.py Thu Feb 03 20:23:00 2011 -0800
@@ -43,7 +43,7 @@
physmem = PhysicalMemory(),
membus = Bus())
system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz'
root = Root(system = system)
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