changeset 3b4d595397fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=3b4d595397fb
description:
inorder: activity tracking bug
Previous code was marking CPU activity on almost every cycle due to a
bug in
tracking the status of pipeline stages. This disables the CPU from
sleeping
on long latency stalls and increases simulation time
diffstat:
src/cpu/inorder/first_stage.cc | 9 ++++++-
src/cpu/inorder/pipeline_stage.cc | 40 +++++++++++++++++++++++++-------------
2 files changed, 33 insertions(+), 16 deletions(-)
diffs (136 lines):
diff -r d3e6ebcccabf -r 3b4d595397fb src/cpu/inorder/first_stage.cc
--- a/src/cpu/inorder/first_stage.cc Thu Feb 03 21:47:58 2011 -0800
+++ b/src/cpu/inorder/first_stage.cc Fri Feb 04 00:08:13 2011 -0500
@@ -126,8 +126,10 @@
if (tid >= 0) {
DPRINTF(InOrderStage, "Processing [tid:%i]\n",tid);
processThread(status_change, tid);
+ DPRINTF(InOrderStage, "Done Processing [tid:%i]\n",tid);
} else {
DPRINTF(InOrderStage, "No more threads to fetch from.\n");
+ break;
}
}
@@ -148,7 +150,7 @@
{
bool all_reqs_completed = true;
- for (int insts_fetched = 0;
+ for (int insts_fetched = instsProcessed;
insts_fetched < stageWidth && canSendInstToStage(1);
insts_fetched++) {
@@ -200,8 +202,11 @@
"list.\n", tid, inst->seqNum);
insts[tid].push(inst);
}
+ block(tid);
break;
} else if (!insts[tid].empty()){
+ DPRINTF(InOrderStage, "[tid:%u]: [sn:%u] Finished all "
+ "requests for this stage.\n", tid, inst->seqNum);
insts[tid].pop();
}
@@ -210,7 +215,7 @@
// Record that stage has written to the time buffer for activity
// tracking.
- if (toNextStageIndex) {
+ if (instsProcessed) {
wroteToTimeBuffer = true;
}
}
diff -r d3e6ebcccabf -r 3b4d595397fb src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Thu Feb 03 21:47:58 2011 -0800
+++ b/src/cpu/inorder/pipeline_stage.cc Fri Feb 04 00:08:13 2011 -0500
@@ -281,14 +281,14 @@
// signalled fetch to unblock. In that case, there is no need to tell
// fetch to block.
if (stageStatus[tid] != Blocked) {
- // Set the status to Blocked.
+ if (stageStatus[tid] != Unblocking) {
+ wroteToTimeBuffer = true;
+ }
+
stageStatus[tid] = Blocked;
- if (stageStatus[tid] != Unblocking) {
- if (prevStageValid)
- toPrevStages->stageBlock[stageNum][tid] = true;
- wroteToTimeBuffer = true;
- }
+ if (prevStageValid)
+ toPrevStages->stageBlock[stageNum][tid] = true;
return true;
}
@@ -304,12 +304,12 @@
"next stage.\n", tid);
if (stageStatus[tid] != Blocked) {
- // Set the status to Blocked.
- stageStatus[tid] = Blocked;
-
if (stageStatus[tid] != Unblocking) {
wroteToTimeBuffer = true;
}
+
+ // Set the status to Blocked.
+ stageStatus[tid] = Blocked;
}
}
@@ -595,18 +595,26 @@
{
if (prevStageValid) {
int insts_from_prev_stage = prevStage->size;
+ int insts_from_cur_stage = skidSize();
+ DPRINTF(InOrderStage, "%i insts available from stage buffer %i. Stage "
+ "currently has %i insts from last cycle.\n",
+ insts_from_prev_stage, prevStageQueue->id(),
+ insts_from_cur_stage);
- DPRINTF(InOrderStage, "%i insts available from stage buffer %i.\n",
- insts_from_prev_stage, prevStageQueue->id());
-
+ int inserted_insts = 0;
for (int i = 0; i < insts_from_prev_stage; ++i) {
+ if (inserted_insts + insts_from_cur_stage == stageWidth) {
+ DPRINTF(InOrderStage, "Stage %i has accepted all insts "
+ "possible for this tick.\n");
+ break;
+ }
if (prevStage->insts[i]->isSquashed()) {
DPRINTF(InOrderStage, "[tid:%i]: Ignoring squashed [sn:%i], "
"not inserting into stage buffer.\n",
prevStage->insts[i]->readTid(),
prevStage->insts[i]->seqNum);
-
+ prevStage->size--;
continue;
}
@@ -622,7 +630,11 @@
prevStage->insts[i] = cpu->dummyBufferInst;
+ prevStage->size--;
+
+ inserted_insts++;
}
+ assert(prevStage->size == 0);
}
}
@@ -937,7 +949,7 @@
// Record that stage has written to the time buffer for activity
// tracking.
- if (toNextStageIndex) {
+ if (instsProcessed) {
wroteToTimeBuffer = true;
}
}
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