changeset d9e8b1fd1a9f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d9e8b1fd1a9f
description:
mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters
for
McPAT
diffstat:
src/cpu/BaseCPU.py | 2 +
src/cpu/base.cc | 2 +
src/cpu/base.hh | 2 +
src/cpu/o3/commit.hh | 6 ++
src/cpu/o3/commit_impl.hh | 34 ++++++++++++
src/cpu/o3/cpu.cc | 50 ++++++++++++++++++-
src/cpu/o3/cpu.hh | 12 ++++
src/cpu/o3/iew_impl.hh | 1 +
src/cpu/o3/inst_queue.hh | 10 +++
src/cpu/o3/inst_queue_impl.hh | 61 ++++++++++++++++++++++-
src/cpu/o3/rename.hh | 2 +
src/cpu/o3/rename_impl.hh | 9 +++
src/cpu/o3/rob.hh | 8 +++
src/cpu/o3/rob_impl.hh | 20 +++++++
src/cpu/simple/atomic.cc | 1 +
src/cpu/simple/base.cc | 110 +++++++++++++++++++++++++++++++++++++++++-
src/cpu/simple/base.hh | 46 +++++++++++++++++-
src/cpu/simple/timing.cc | 1 +
src/sim/System.py | 3 +
src/sim/system.cc | 13 ++++-
src/sim/system.hh | 6 ++
21 files changed, 393 insertions(+), 6 deletions(-)
diffs (truncated from 1006 to 300 lines):
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/BaseCPU.py Sun Feb 06 22:14:17 2011 -0800
@@ -1,4 +1,5 @@
# Copyright (c) 2005-2008 The Regents of The University of Michigan
+# Copyright (c) 2011 Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -25,6 +26,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Nathan Binkert
+# Rick Strong
import sys
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/base.cc
--- a/src/cpu/base.cc Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/base.cc Sun Feb 06 22:14:17 2011 -0800
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
*
* Authors: Steve Reinhardt
* Nathan Binkert
+ * Rick Strong
*/
#include <iostream>
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/base.hh
--- a/src/cpu/base.hh Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/base.hh Sun Feb 06 22:14:17 2011 -0800
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
*
* Authors: Steve Reinhardt
* Nathan Binkert
+ * Rick Strong
*/
#ifndef __CPU_BASE_HH__
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/o3/commit.hh Sun Feb 06 22:14:17 2011 -0800
@@ -473,6 +473,12 @@
Stats::Vector statComMembars;
/** Total number of committed branches. */
Stats::Vector statComBranches;
+ /** Total number of floating point instructions */
+ Stats::Vector statComFloating;
+ /** Total number of integer instructions */
+ Stats::Vector statComInteger;
+ /** Total number of function calls */
+ Stats::Vector statComFunctionCalls;
/** Number of cycles where the commit bandwidth limit is reached. */
Stats::Scalar commitEligibleSamples;
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/o3/commit_impl.hh Sun Feb 06 22:14:17 2011 -0800
@@ -230,6 +230,27 @@
.flags(total)
;
+ statComFloating
+ .init(cpu->numThreads)
+ .name(name() + ".COM:fp_insts")
+ .desc("Number of committed floating point instructions.")
+ .flags(total)
+ ;
+
+ statComInteger
+ .init(cpu->numThreads)
+ .name(name()+".COM:int_insts")
+ .desc("Number of committed integer instructions.")
+ .flags(total)
+ ;
+
+ statComFunctionCalls
+ .init(cpu->numThreads)
+ .name(name()+".COM:function_calls")
+ .desc("Number of function calls committed.")
+ .flags(total)
+ ;
+
commitEligible
.init(cpu->numThreads)
.name(name() + ".COM:bw_limited")
@@ -1321,6 +1342,19 @@
if (inst->isMemBarrier()) {
statComMembars[tid]++;
}
+
+ // Integer Instruction
+ if (inst->isInteger())
+ statComInteger[tid]++;
+
+ // Floating Point Instruction
+ if (inst->isFloating())
+ statComFloating[tid]++;
+
+ // Function Calls
+ if (inst->isCall())
+ statComFunctionCalls[tid]++;
+
}
////////////////////////////////////////
diff -r 46e9b3bf447f -r d9e8b1fd1a9f src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sun Feb 06 22:14:17 2011 -0800
+++ b/src/cpu/o3/cpu.cc Sun Feb 06 22:14:17 2011 -0800
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
*
* Authors: Kevin Lim
* Korey Sewell
+ * Rick Strong
*/
#include "config/full_system.hh"
@@ -480,6 +482,37 @@
this->rename.regStats();
this->iew.regStats();
this->commit.regStats();
+ this->rob.regStats();
+
+ intRegfileReads
+ .name(name() + ".int_regfile_reads")
+ .desc("number of integer regfile reads")
+ .prereq(intRegfileReads);
+
+ intRegfileWrites
+ .name(name() + ".int_regfile_writes")
+ .desc("number of integer regfile writes")
+ .prereq(intRegfileWrites);
+
+ fpRegfileReads
+ .name(name() + ".fp_regfile_reads")
+ .desc("number of floating regfile reads")
+ .prereq(fpRegfileReads);
+
+ fpRegfileWrites
+ .name(name() + ".fp_regfile_writes")
+ .desc("number of floating regfile writes")
+ .prereq(fpRegfileWrites);
+
+ miscRegfileReads
+ .name(name() + ".misc_regfile_reads")
+ .desc("number of misc regfile reads")
+ .prereq(miscRegfileReads);
+
+ miscRegfileWrites
+ .name(name() + ".misc_regfile_writes")
+ .desc("number of misc regfile writes")
+ .prereq(miscRegfileWrites);
}
template <class Impl>
@@ -1184,6 +1217,7 @@
TheISA::MiscReg
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
+ miscRegfileReads++;
return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
@@ -1200,6 +1234,7 @@
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, ThreadID tid)
{
+ miscRegfileWrites++;
this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
}
@@ -1207,6 +1242,7 @@
uint64_t
FullO3CPU<Impl>::readIntReg(int reg_idx)
{
+ intRegfileReads++;
return regFile.readIntReg(reg_idx);
}
@@ -1214,6 +1250,7 @@
FloatReg
FullO3CPU<Impl>::readFloatReg(int reg_idx)
{
+ fpRegfileReads++;
return regFile.readFloatReg(reg_idx);
}
@@ -1221,6 +1258,7 @@
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
{
+ fpRegfileReads++;
return regFile.readFloatRegBits(reg_idx);
}
@@ -1228,6 +1266,7 @@
void
FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
{
+ intRegfileWrites++;
regFile.setIntReg(reg_idx, val);
}
@@ -1235,6 +1274,7 @@
void
FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
+ fpRegfileWrites++;
regFile.setFloatReg(reg_idx, val);
}
@@ -1242,6 +1282,7 @@
void
FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
+ fpRegfileWrites++;
regFile.setFloatRegBits(reg_idx, val);
}
@@ -1249,6 +1290,7 @@
uint64_t
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
+ intRegfileReads++;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
return regFile.readIntReg(phys_reg);
@@ -1258,6 +1300,7 @@
float
FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
{
+ fpRegfileReads++;
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1268,6 +1311,7 @@
uint64_t
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
{
+ fpRegfileReads++;
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1278,6 +1322,7 @@
void
FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
{
+ intRegfileWrites++;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
regFile.setIntReg(phys_reg, val);
@@ -1287,6 +1332,7 @@
void
FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
{
+ fpRegfileWrites++;
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1297,6 +1343,7 @@
void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
{
+ fpRegfileWrites++;
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@@ -1364,9 +1411,10 @@
thread[tid]->numInsts++;
committedInsts[tid]++;
totalCommittedInsts++;
-
+ system->totalNumInsts++;
// Check for instruction-count-based events.
comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
+ system->instEventQueue.serviceEvents(system->totalNumInsts);
}
template <class Impl>
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