changeset 5ccd97218ca0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5ccd97218ca0
description:
ruby: Assert for x86 misaligned access
This patch ensures only aligned access are passed to ruby and includes
a fix
to the DPRINTF address print.
diffstat:
src/mem/ruby/system/RubyPort.cc | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diffs (22 lines):
diff -r 00ad807ed2ca -r 5ccd97218ca0 src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:18 2011 -0800
@@ -226,6 +226,9 @@
pkt->getSize(), pc, type,
RubyAccessMode_Supervisor, pkt);
+ assert(Address(ruby_request.paddr).getOffset() + ruby_request.len <=
+ RubySystem::getBlockSizeBytes());
+
// Submit the ruby request
RequestStatus requestStatus = ruby_port->makeRequest(ruby_request);
@@ -237,7 +240,7 @@
}
DPRINTF(MemoryAccess,
- "Request for address #x did not issue because %s\n",
+ "Request for address %#x did not issue because %s\n",
pkt->getAddr(), RequestStatus_to_string(requestStatus));
SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
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