changeset 8a92b39be50e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8a92b39be50e
description:
ruby: Fix RubyPort to properly handle retrys
diffstat:
src/mem/ruby/system/RubyPort.cc | 29 +++++++++++++++++++++++++++++
src/mem/ruby/system/RubyPort.hh | 25 +++++++++++++++++++++++++
src/mem/ruby/system/Sequencer.cc | 1 -
src/mem/ruby/system/Sequencer.hh | 2 --
src/mem/ruby/system/Sequencer.py | 2 +-
5 files changed, 55 insertions(+), 4 deletions(-)
diffs (161 lines):
diff -r eee578ed2130 -r 8a92b39be50e src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:18 2011 -0800
@@ -49,6 +49,8 @@
m_request_cnt = 0;
pio_port = NULL;
physMemPort = NULL;
+
+ m_usingRubyTester = p->using_ruby_tester;
}
void
@@ -108,6 +110,7 @@
{
DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
ruby_port = _port;
+ _onRetryList = false;
}
Tick
@@ -256,9 +259,18 @@
// Otherwise, we need to delete the senderStatus we just created and return
// false.
if (requestStatus == RequestStatus_Issued) {
+ DPRINTF(MemoryAccess, "Request %x issued\n", pkt->getAddr());
return true;
}
+ //
+ // Unless one is using the ruby tester, record the stalled M5 port for
+ // later retry when the sequencer becomes free.
+ //
+ if (!ruby_port->m_usingRubyTester) {
+ ruby_port->addToRetryList(this);
+ }
+
DPRINTF(MemoryAccess,
"Request for address %#x did not issue because %s\n",
pkt->getAddr(), RequestStatus_to_string(requestStatus));
@@ -283,6 +295,23 @@
delete senderState;
port->hitCallback(pkt);
+
+ //
+ // If we had to stall the M5Ports, wake them up because the sequencer
+ // likely has free resources now.
+ //
+ if (waitingOnSequencer) {
+ for (std::list<M5Port*>::iterator i = retryList.begin();
+ i != retryList.end(); ++i) {
+ (*i)->sendRetry();
+ (*i)->onRetryList(false);
+ DPRINTF(MemoryAccess,
+ "Sequencer may now be free. SendRetry to port %s\n",
+ (*i)->name());
+ }
+ retryList.clear();
+ waitingOnSequencer = false;
+ }
}
void
diff -r eee578ed2130 -r 8a92b39be50e src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.hh Sun Feb 06 22:14:18 2011 -0800
@@ -50,12 +50,19 @@
{
private:
RubyPort *ruby_port;
+ bool _onRetryList;
public:
M5Port(const std::string &_name, RubyPort *_port);
bool sendTiming(PacketPtr pkt);
void hitCallback(PacketPtr pkt);
unsigned deviceBlockSize() const;
+
+ bool onRetryList()
+ { return _onRetryList; }
+
+ void onRetryList(bool newVal)
+ { _onRetryList = newVal; }
protected:
virtual bool recvTiming(PacketPtr pkt);
@@ -118,14 +125,32 @@
AbstractController* m_controller;
MessageBuffer* m_mandatory_q_ptr;
PioPort* pio_port;
+ bool m_usingRubyTester;
private:
+ void addToRetryList(M5Port * port)
+ {
+ if (!port->onRetryList()) {
+ port->onRetryList(true);
+ retryList.push_back(port);
+ waitingOnSequencer = true;
+ }
+ }
+
uint16_t m_port_id;
uint64_t m_request_cnt;
M5Port* physMemPort;
PhysicalMemory* physmem;
+
+ //
+ // Based on similar code in the M5 bus. Stores pointers to those ports
+ // that should be called when the Sequencer becomes available after a
stall.
+ //
+ std::list<M5Port*> retryList;
+
+ bool waitingOnSequencer;
};
#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
diff -r eee578ed2130 -r 8a92b39be50e src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/Sequencer.cc Sun Feb 06 22:14:18 2011 -0800
@@ -72,7 +72,6 @@
m_dataCache_ptr = p->dcache;
m_max_outstanding_requests = p->max_outstanding_requests;
m_deadlock_threshold = p->deadlock_threshold;
- m_usingRubyTester = p->using_ruby_tester;
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
diff -r eee578ed2130 -r 8a92b39be50e src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/Sequencer.hh Sun Feb 06 22:14:18 2011 -0800
@@ -152,8 +152,6 @@
int m_load_waiting_on_store_cycles;
int m_load_waiting_on_load_cycles;
- bool m_usingRubyTester;
-
class SequencerWakeupEvent : public Event
{
private:
diff -r eee578ed2130 -r 8a92b39be50e src/mem/ruby/system/Sequencer.py
--- a/src/mem/ruby/system/Sequencer.py Sun Feb 06 22:14:18 2011 -0800
+++ b/src/mem/ruby/system/Sequencer.py Sun Feb 06 22:14:18 2011 -0800
@@ -39,6 +39,7 @@
pio_port = Port("Ruby_pio_port")
physmem = Param.PhysicalMemory("")
physMemPort = Port("port to physical memory")
+ using_ruby_tester = Param.Bool(False, "")
class RubySequencer(RubyPort):
type = 'RubySequencer'
@@ -49,7 +50,6 @@
"max requests (incl. prefetches) outstanding")
deadlock_threshold = Param.Int(500000,
"max outstanding cycles for a request before deadlock/livelock
declared")
- using_ruby_tester = Param.Bool(False, "")
class DMASequencer(RubyPort):
type = 'DMASequencer'
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