changeset 70b56a9ac1b2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=70b56a9ac1b2
description:
dev: fixed bugs to extend interrupt capability beyond 15 cores
diffstat:
src/arch/x86/interrupts.cc | 7 +++++++
src/dev/x86/i82094aa.cc | 22 ++++++++++++++++++----
src/dev/x86/i82094aa.hh | 2 ++
src/dev/x86/intdev.cc | 9 +++++++++
src/dev/x86/intdev.hh | 10 ++--------
5 files changed, 38 insertions(+), 12 deletions(-)
diffs (126 lines):
diff -r a9f05ab40763 -r 70b56a9ac1b2 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/arch/x86/interrupts.cc Sun Feb 06 22:14:18 2011 -0800
@@ -294,7 +294,14 @@
void
X86ISA::Interrupts::init()
{
+ //
+ // The local apic must register its address ranges on both its pio port
+ // via the basicpiodevice(piodevice) init() function and its int port
+ // that it inherited from IntDev. Note IntDev is not a SimObject itself.
+ //
BasicPioDevice::init();
+ IntDev::init();
+
Pc * pc = dynamic_cast<Pc *>(platform);
assert(pc);
pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
diff -r a9f05ab40763 -r 70b56a9ac1b2 src/dev/x86/i82094aa.cc
--- a/src/dev/x86/i82094aa.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/dev/x86/i82094aa.cc Sun Feb 06 22:14:18 2011 -0800
@@ -41,9 +41,12 @@
latency(p->pio_latency), pioAddr(p->pio_addr),
extIntPic(p->external_int_pic), lowestPriorityOffset(0)
{
- // This assumes there's only one I/O APIC in the system
+ // This assumes there's only one I/O APIC in the system and since the apic
+ // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
+ // be less than 0xff
+
+ assert(p->apic_id < 0xff);
initialApicId = id = p->apic_id;
- assert(id <= 0xf);
arbId = id;
regSel = 0;
RedirTableEntry entry = 0;
@@ -54,6 +57,17 @@
}
}
+void
+X86ISA::I82094AA::init()
+{
+ // The io apic must register its address ranges on both its pio port
+ // via the piodevice init() function and its int port that it inherited
+ // from IntDev. Note IntDev is not a SimObject itself.
+
+ PioDevice::init();
+ IntDev::init();
+}
+
Tick
X86ISA::I82094AA::read(PacketPtr pkt)
{
@@ -96,11 +110,11 @@
X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
{
if (offset == 0x0) {
- id = bits(value, 27, 24);
+ id = bits(value, 31, 24);
} else if (offset == 0x1) {
// The IOAPICVER register is read only.
} else if (offset == 0x2) {
- arbId = bits(value, 27, 24);
+ arbId = bits(value, 31, 24);
} else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
int index = (offset - 0x10) / 2;
if (offset % 2) {
diff -r a9f05ab40763 -r 70b56a9ac1b2 src/dev/x86/i82094aa.hh
--- a/src/dev/x86/i82094aa.hh Sun Feb 06 22:14:18 2011 -0800
+++ b/src/dev/x86/i82094aa.hh Sun Feb 06 22:14:18 2011 -0800
@@ -98,6 +98,8 @@
I82094AA(Params *p);
+ void init();
+
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);
diff -r a9f05ab40763 -r 70b56a9ac1b2 src/dev/x86/intdev.cc
--- a/src/dev/x86/intdev.cc Sun Feb 06 22:14:18 2011 -0800
+++ b/src/dev/x86/intdev.cc Sun Feb 06 22:14:18 2011 -0800
@@ -48,6 +48,15 @@
}
}
+void
+X86ISA::IntDev::init()
+{
+ if (!intPort) {
+ panic("Int port not connected to anything!");
+ }
+ intPort->sendStatusChange(Port::RangeChange);
+}
+
X86ISA::IntSourcePin *
X86IntSourcePinParams::create()
{
diff -r a9f05ab40763 -r 70b56a9ac1b2 src/dev/x86/intdev.hh
--- a/src/dev/x86/intdev.hh Sun Feb 06 22:14:18 2011 -0800
+++ b/src/dev/x86/intdev.hh Sun Feb 06 22:14:18 2011 -0800
@@ -84,14 +84,6 @@
// need to be moved into a subclass.
void sendMessage(ApicList apics,
TriggerIntMessage message, bool timing);
-
- void recvStatusChange(Status status)
- {
- if (status == RangeChange) {
- sendStatusChange(Port::RangeChange);
- }
- }
-
};
IntPort * intPort;
@@ -110,6 +102,8 @@
virtual ~IntDev()
{}
+ virtual void init();
+
virtual void
signalInterrupt(int line)
{
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