changeset bc39c93a5519 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bc39c93a5519
description:
mem: Added support for Null data packet
The packet now identifies whether static or dynamic data has been
allocated and
is used by Ruby to determine whehter to copy the data pointer into the
ruby
request. Subsequently, Ruby can be told not to update phys memory when
receiving packets.
diffstat:
src/mem/packet.hh | 5 ++---
src/mem/ruby/system/DMASequencer.cc | 12 ++++++++----
src/mem/ruby/system/RubyPort.cc | 22 +++++++++++++---------
src/mem/ruby/system/RubyPort.hh | 5 ++++-
src/mem/ruby/system/Sequencer.py | 4 +++-
5 files changed, 30 insertions(+), 18 deletions(-)
diffs (174 lines):
diff -r eee5bb0fb8ea -r bc39c93a5519 src/mem/packet.hh
--- a/src/mem/packet.hh Sun Feb 06 22:14:19 2011 -0800
+++ b/src/mem/packet.hh Sun Feb 06 22:14:19 2011 -0800
@@ -681,9 +681,9 @@
*/
template <typename T>
T*
- getPtr()
+ getPtr(bool null_ok = false)
{
- assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
+ assert(null_ok || flags.isSet(STATIC_DATA|DYNAMIC_DATA));
return (T*)data;
}
@@ -768,7 +768,6 @@
data = new uint8_t[getSize()];
}
-
/**
* Check a functional request against a memory value represented
* by a base/size pair and an associated data array. If the
diff -r eee5bb0fb8ea -r bc39c93a5519 src/mem/ruby/system/DMASequencer.cc
--- a/src/mem/ruby/system/DMASequencer.cc Sun Feb 06 22:14:19 2011 -0800
+++ b/src/mem/ruby/system/DMASequencer.cc Sun Feb 06 22:14:19 2011 -0800
@@ -97,8 +97,10 @@
msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
len : RubySystem::getBlockSizeBytes() - offset;
- if (write) {
- msg->getDataBlk().setData(data, offset, msg->getLen());
+ if (write && (data != NULL)) {
+ if (active_request.data != NULL) {
+ msg->getDataBlk().setData(data, offset, msg->getLen());
+ }
}
assert(m_mandatory_q_ptr != NULL);
@@ -160,8 +162,10 @@
if (active_request.bytes_completed == 0)
offset = active_request.start_paddr & m_data_block_mask;
assert(active_request.write == false);
- memcpy(&active_request.data[active_request.bytes_completed],
- dblk.getData(offset, len), len);
+ if (active_request.data != NULL) {
+ memcpy(&active_request.data[active_request.bytes_completed],
+ dblk.getData(offset, len), len);
+ }
issueNext();
}
diff -r eee5bb0fb8ea -r bc39c93a5519 src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:19 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Sun Feb 06 22:14:19 2011 -0800
@@ -51,6 +51,7 @@
physMemPort = NULL;
m_usingRubyTester = p->using_ruby_tester;
+ access_phys_mem = p->access_phys_mem;
}
void
@@ -64,7 +65,8 @@
RubyPort::getPort(const std::string &if_name, int idx)
{
if (if_name == "port") {
- return new M5Port(csprintf("%s-port%d", name(), idx), this);
+ return new M5Port(csprintf("%s-port%d", name(), idx), this,
+ access_phys_mem);
}
if (if_name == "pio_port") {
@@ -80,7 +82,8 @@
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this);
+ physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
+ access_phys_mem);
return physMemPort;
}
@@ -105,12 +108,13 @@
}
RubyPort::M5Port::M5Port(const std::string &_name,
- RubyPort *_port)
+ RubyPort *_port, bool _access_phys_mem)
: SimpleTimingPort(_name, _port)
{
DPRINTF(Ruby, "creating port from ruby sequcner to cpu %s\n", _name);
ruby_port = _port;
_onRetryList = false;
+ access_phys_mem = _access_phys_mem;
}
Tick
@@ -245,7 +249,7 @@
}
}
- RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(),
+ RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true),
pkt->getSize(), pc, type,
RubyAccessMode_Supervisor, pkt);
@@ -320,9 +324,10 @@
bool needsResponse = pkt->needsResponse();
//
- // All responses except failed SC operations access M5 physical memory
+ // Unless specified at configuraiton, all responses except failed SC
+ // operations access M5 physical memory.
//
- bool accessPhysMem = true;
+ bool accessPhysMem = access_phys_mem;
if (pkt->isLLSC()) {
if (pkt->isWrite()) {
@@ -351,13 +356,12 @@
if (accessPhysMem) {
ruby_port->physMemPort->sendAtomic(pkt);
+ } else {
+ pkt->makeResponse();
}
// turn packet around to go back to requester if response expected
if (needsResponse) {
- // sendAtomic() should already have turned packet into
- // atomic response
- assert(pkt->isResponse());
DPRINTF(MemoryAccess, "Sending packet back over port\n");
sendTiming(pkt);
} else {
diff -r eee5bb0fb8ea -r bc39c93a5519 src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Sun Feb 06 22:14:19 2011 -0800
+++ b/src/mem/ruby/system/RubyPort.hh Sun Feb 06 22:14:19 2011 -0800
@@ -51,9 +51,11 @@
private:
RubyPort *ruby_port;
bool _onRetryList;
+ bool access_phys_mem;
public:
- M5Port(const std::string &_name, RubyPort *_port);
+ M5Port(const std::string &_name, RubyPort *_port,
+ bool _access_phys_mem);
bool sendTiming(PacketPtr pkt);
void hitCallback(PacketPtr pkt);
unsigned deviceBlockSize() const;
@@ -151,6 +153,7 @@
std::list<M5Port*> retryList;
bool waitingOnSequencer;
+ bool access_phys_mem;
};
#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
diff -r eee5bb0fb8ea -r bc39c93a5519 src/mem/ruby/system/Sequencer.py
--- a/src/mem/ruby/system/Sequencer.py Sun Feb 06 22:14:19 2011 -0800
+++ b/src/mem/ruby/system/Sequencer.py Sun Feb 06 22:14:19 2011 -0800
@@ -40,7 +40,9 @@
physmem = Param.PhysicalMemory("")
physMemPort = Port("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
-
+ access_phys_mem = Param.Bool(True,
+ "should the rubyport atomically update phys_mem")
+
class RubySequencer(RubyPort):
type = 'RubySequencer'
cxx_class = 'Sequencer'
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